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ESD TVS Diode Selection Calculator

Calculate TVS diode clamping voltage, breakdown voltage, and peak pulse power. Select ESD protection for IEC 61000-4-2 circuit design.

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Formula

Ipp=VESDRHBM,Ppk=Vclamp×IppI_{pp} = \frac{V_{ESD}}{R_{HBM}},\quad P_{pk} = V_{clamp} \times I_{pp}

Reference: JEDEC JESD22-A114 HBM / IEC 61000-4-2

Vwm— Working voltage (V)
VBR— Breakdown voltage (V)
Vclamp— Clamp voltage (V)
R_HBM— HBM discharge resistance 1500Ω (Ω)

How It Works

The ESD TVS Diode Calculator computes breakdown voltage, clamping voltage, and power handling for transient voltage suppressor selection — essential for protecting 3.3V/5V logic, USB/HDMI interfaces, and automotive electronics from IEC 61000-4-2 ESD events. Hardware engineers use this to prevent IC damage from 2-15 kV electrostatic discharges that occur during normal product handling.

Per JEDEC JESD22-A114 and ON Semiconductor application notes, TVS diode selection requires matching three parameters: (1) Standoff voltage V_WM > operating voltage with 10% margin; (2) Clamping voltage V_cl at peak current < IC absolute maximum rating; (3) Peak pulse power P_pk > V_cl x I_pk during the ESD event. For IEC 61000-4-2 Level 4 (8 kV contact), I_pk = 24 A for approximately 1 ns.

The Human Body Model (HBM) uses 100 pF / 1500 ohm, producing I_pk = V_ESD / 1500 at initial surge. For 2 kV HBM: I_pk = 2000/1500 = 1.33 A. Peak power P_pk = V_cl x I_pk; for a TVS with V_cl = 8V: P_pk = 8 x 1.33 = 10.6 W. TVS devices are rated for peak power (typically 400-600 W for SOD-323, 1500 W for SMC) assuming the short pulse duration per JEDEC.

Per Nexperia and Littelfuse datasheets, TVS response time is <1 ns for silicon avalanche diodes. Capacitance ranges from 0.1 pF (low-cap for high-speed) to 100+ pF (standard power TVS). For USB 3.0+, specify <0.5 pF to maintain signal integrity; for power rails, higher capacitance is acceptable.

Worked Example

Problem

Select TVS to protect 3.3V microcontroller GPIO from 2 kV HBM ESD. IC absolute maximum is 4.0V on any pin.

Solution per JEDEC:

  1. Operating voltage: 3.3V; standoff V_WM > 3.3 x 1.1 = 3.63V; select 5V standoff TVS
  2. HBM parameters: 100 pF, 1500 ohm, 2 kV
  3. Peak current: I_pk = 2000/1500 = 1.33 A
  4. Required V_cl: < 4.0V (IC absolute max), select TVS with V_cl < 4.0V at 1.33 A
  5. Typical 5V standoff TVS: V_cl approximately 9-12V at 1 A — TOO HIGH for 4.0V max!
  6. Need low-clamping TVS: Select PESD3V3L1BA (3.3V TVS, V_cl = 6.5V at 1 A)
  7. Still too high? Use bidirectional TVS PESD3V3S1UB (V_cl = 5.5V at 1 A) — meets 4.0V? No.
  8. Solution: Add 100 ohm series resistor to GPIO; this drops (1.33A x 100) = 133mV, allowing V_cl up to 4.13V
Alternative: Select 3.3V rail-to-rail TVS with lower V_cl, or use Schottky diode clamp to Vcc rail if voltage headroom exists.

Solution

Add 100 ohm series resistor to GPIO; this drops (1.33A x 100) = 133mV, allowing V_cl up to 4.13V

Alternative: Select 3.3V rail-to-rail TVS with lower V_cl, or use Schottky diode clamp to Vcc rail if voltage headroom exists.

Practical Tips

  • ✓Choose TVS with V_cl at least 20% below IC absolute max — per ON Semi, ESD current varies +/-20% in real events; margin prevents marginal damage that causes latent failures.
  • ✓Use bidirectional TVS for signals that swing below ground — per Nexperia, unidirectional TVS only clamps positive transients; negative ESD can damage IC through substrate injection.
  • ✓Place TVS as close as possible to connector/IC pin being protected — per JEDEC, every 10mm of trace adds approximately 10 nH inductance that creates V = L x dI/dt overshoot during ESD event.

Common Mistakes

  • ✗Selecting TVS based on standoff voltage matching operating voltage — per Littelfuse, V_cl is typically 1.3-1.8x higher than standoff voltage at rated current. A 5V standoff TVS has V_cl approximately 8-9V, damaging 3.3V CMOS with 4.0V max rating.
  • ✗Ignoring peak current in power calculation — per JEDEC, HBM pulse has 1.33 A peak but IEC 61000-4-2 has 24 A peak at same voltage. Power rating must match the ESD model being protected against, not just voltage.
  • ✗Using standard TVS on high-speed signals — per USB-IF, standard TVS (5-50 pF) causes 10-20% eye closure at 480 Mbps and complete signal failure at 5+ Gbps. Specify low-cap TVS (<1 pF) for any signal above 100 MHz.

Frequently Asked Questions

Per Littelfuse: TVS diodes protect ICs from transient overvoltage by clamping voltage to a safe level while absorbing surge energy. They operate in avalanche breakdown mode during ESD events, conducting current through the device instead of through the protected IC. Response time <1 ns provides protection during the initial fast rise of ESD pulses.
Per JEDEC: TVS selection prioritizes: (1) Clamping voltage at peak surge current, not just breakdown voltage; (2) Peak pulse power rating for the specific ESD waveform (HBM, IEC 61000-4-2, IEC 61000-4-5); (3) Capacitance for signal integrity; (4) Response time (<1 ns required). Regular diodes are selected for DC voltage, forward current, and reverse recovery — different parameters entirely.
Per ON Semi: Unidirectional TVS clamps positive voltages above V_cl and acts as forward diode (0.7V drop) for negative voltages. Bidirectional TVS clamps both polarities at +/-V_cl symmetrically. Use bidirectional for: AC signals, signals that swing below ground, data lines with unknown polarity. Use unidirectional for: DC power rails, signals referenced to fixed ground.
Per USB-IF: TVS capacitance loads the signal line, causing impedance mismatch and reflection. At 5 Gbps, 1 pF capacitance causes approximately 5% eye closure; 5 pF causes approximately 20%. For high-speed interfaces (USB 3.0+, HDMI 2.0+, PCIe), specify TVS with <0.5 pF. For power rails and low-speed signals (<100 MHz), capacitance is less critical — higher-capacitance TVS often has better clamping.
Per IEC 61000-4-2 test procedure: (1) Apply ESD discharges at specified levels to all accessible points; (2) Verify no functional upset or damage; (3) For marginal passes, use oscilloscope with high-bandwidth current probe to measure actual V_cl during discharge. If V_cl exceeds IC ratings, TVS selection or layout needs improvement. Pre-compliance ESD generators (Teseq, EMC Partner) enable in-house testing.

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