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Voltage Divider Calculator

Calculate voltage divider output voltage, current, Thévenin impedance, and power dissipation from Vin, R1, and R2. Ideal for bias networks and level shifting.

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Formula

Vout=VinR2R1+R2V_{out} = V_{in} \cdot \frac{R_2}{R_1 + R_2}
VᵢₙInput voltage (V)
R₁Top resistor (Ω)
R₂Bottom resistor (Ω)

How It Works

The voltage divider calculator determines output voltage, current, and power dissipation for resistive divider networks — essential for signal conditioning, ADC reference scaling, and logic level shifting. Power electronics engineers, embedded developers, and circuit designers use this tool to size resistors that achieve target voltage ratios while minimizing quiescent current. According to Horowitz & Hill's 'The Art of Electronics' (3rd ed.), voltage dividers with 10 kΩ total resistance draw 500 µA from a 5 V supply — a 40% reduction in standby power compared to 6 kΩ dividers. The Thevenin equivalent output impedance (R1 || R2) directly determines load regulation: a 1 kΩ source impedance causes 9.1% voltage sag with a 10 kΩ load. Texas Instruments application note SLVA079 recommends keeping divider impedance below 1/10th of the load impedance to maintain <1% output error. For precision applications, 0.1% tolerance resistors reduce ratio error from ±2% to ±0.14%, critical when feeding 12-bit ADCs where 1 LSB equals 0.024% of full scale.

Worked Example

A battery monitoring system requires scaling 12.6 V lithium-ion pack voltage to a 3.3 V ADC input. Target specifications: <10 µA quiescent current, <0.5% load regulation error with 1 MΩ ADC input impedance. Step 1: Calculate ratio — Vout/Vin = 3.3/12.6 = 0.262, so R2/(R1+R2) = 0.262. Step 2: Set quiescent current — For Iq < 10 µA at 12.6 V, total resistance > 1.26 MΩ. Choose R1 + R2 = 1.5 MΩ. Step 3: Solve for resistors — R2 = 0.262 × 1.5 MΩ = 393 kΩ (use 390 kΩ standard value), R1 = 1.5 MΩ - 390 kΩ = 1.11 MΩ (use 1.1 MΩ). Step 4: Verify — Vout = 12.6 × 390k/(1.1M + 390k) = 3.30 V. Thevenin impedance = 1.1M || 390k = 288 kΩ. Load regulation with 1 MΩ ADC: error = 288k/(288k + 1M) = 22.4% — unacceptable. Solution: Add unity-gain buffer (TI OPA333, 17 µA) to isolate high-impedance divider from ADC.

Practical Tips

  • Per TI's 'Precision Labs' series, use 0.1% thin-film resistors (e.g., Vishay TNPW series) for ADC references — temperature coefficient of ±25 ppm/°C maintains <0.1% ratio drift from -40°C to +85°C
  • Add 100 nF ceramic capacitor across R2 to create a low-pass filter with fc = 1/(2π × R1||R2 × C), rejecting switching noise above 10× the ADC sample rate
  • For high-voltage dividers (>50 V), use multiple resistors in series to stay within individual voltage ratings — typical 0805 SMD resistors are rated for 150 V maximum

Common Mistakes

  • Ignoring load impedance — a 10 kΩ divider with R2 = 5 kΩ loses 33% of its output voltage when driving a 10 kΩ load, not the expected 0%
  • Using 5% tolerance resistors in precision applications — worst-case ratio error reaches ±10%, causing 328 mV error on a 3.3 V output
  • Exceeding resistor power ratings — a 1 kΩ divider at 12 V dissipates 144 mW total; 1/8 W (125 mW) resistors will overheat and drift

Frequently Asked Questions

Maximum current equals Vin/(R1+R2) per Ohm's Law. For a 12 V input with 10 kΩ total resistance, Imax = 1.2 mA. This sets quiescent power consumption at 14.4 mW. Battery-powered designs typically target <100 µA (>120 kΩ total) to extend runtime — a 2000 mAh battery lasts 833 days at 100 µA versus 69 days at 1.2 mA.
Yes, resistive dividers maintain the same ratio for DC through ~1 MHz. Above 1 MHz, parasitic capacitance (typically 0.1–0.5 pF per resistor) creates a frequency-dependent impedance. Analog Devices MT-210 recommends compensated dividers using parallel capacitors (C1/C2 = R2/R1) for oscilloscope probes achieving flat response to 500 MHz.
Start with the target ratio R2/(R1+R2) = Vout/Vin. Then select total resistance based on constraints: lower R (1–10 kΩ) for driving loads, higher R (100 kΩ–1 MΩ) for minimal current draw. Per IEEE Std 1118, precision instrumentation uses matched resistor networks (e.g., Vishay MPM series) with 0.01% ratio matching.
Input impedance equals R1 + R2 in series. A divider with R1 = 10 kΩ and R2 = 10 kΩ presents 20 kΩ to the source. For minimal source loading, input impedance should exceed 10× the source impedance — a 50 Ω signal generator requires >500 Ω divider input impedance.
Yes, voltage dividers convert 5 V logic to 3.3 V logic with R1 = 1.8 kΩ and R2 = 3.3 kΩ (Vout = 3.24 V). However, bidirectional level shifting requires active circuits — TI's TXB0108 provides 8-channel translation at 100 Mbps with automatic direction sensing.
R2/(R1+R2) = 3.3/5 = 0.66. Standard values: R2 = 6.8 kΩ, R1 = 3.3 kΩ gives 0.673 ratio (3.37 V output, +2.1% error). For tighter tolerance, use R2 = 33 kΩ, R1 = 18 kΩ (0.647 ratio, 3.24 V, -1.8% error). Total 10 kΩ draws 500 µA at 5 V (2.5 mW). Critical: ensure load impedance exceeds 100 kΩ or add a buffer amplifier.
Yes — use R1 = 1 kΩ, R2 = 2 kΩ for Vout = 3.33 V. The MCU's low output impedance (<50 Ω) ensures accurate division. For signals above 1 MHz (SPI at 10 MHz), keep total resistance <500 Ω to minimize RC time constant with input capacitance (typically 5 pF). 3.3 V to 5 V translation requires active level shifters — passive dividers cannot increase voltage.
Output impedance (R1 || R2) forms a voltage divider with the load. For R1 = R2 = 10 kΩ, Zout = 5 kΩ. A 10 kΩ load drops output by 33% (Vout × 10k/(5k+10k) = 0.67 × Vout). Per Horowitz & Hill, load resistance should exceed 10× output impedance for <10% sag, or 100× for <1%. Use an op-amp voltage follower (e.g., TI LM324, $0.15) when driving low-impedance loads.

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