CAN Bus Bit Timing Calculator
Calculate CAN bus bit timing parameters including prescaler, time quanta, sync segment, propagation segment, and phase buffer segments for a given baud rate and sample point
Formula
How It Works
This calculator determines CAN bus bit timing parameters for automotive and industrial networks. Embedded engineers and automotive system designers use it to configure CAN controllers per ISO 11898-1 (CAN 2.0) and ISO 11898-2 (high-speed physical layer) specifications. The bit time is divided into 4 segments: Sync_Seg (always 1 TQ), Prop_Seg (1-8 TQ for propagation delay compensation), Phase_Seg1 (1-8 TQ), and Phase_Seg2 (1-8 TQ). The sample point, where the bus level is read, should be positioned at 75-87.5% of the bit time per ISO 11898-1:2015 Section 11.3.1.1 (Road vehicles — Controller area network — Part 1: Data link layer and physical signalling) and ISO 11898-2:2016 (Physical medium attachment layer). CAN FD timing is specified in ISO 11898-1:2015 Amendment 1. For a 500 kbps network (the most common automotive rate), bit time is 2 microseconds. With an 80 MHz clock and 8-16 time quanta per bit, achievable prescaler values range from 10-20. CAN FD extends speeds to 2-8 Mbps in the data phase, requiring sample points of 70-80% and tighter oscillator tolerance (0.1% versus 0.5% for classic CAN).
Worked Example
An automotive body control module requires CAN communication at 500 kbps using an S32K144 microcontroller with 80 MHz CAN clock. Per ISO 11898-1 timing requirements: Bit time = 1/500000 = 2 microseconds. Target 16 TQ per bit for fine adjustment. Time quantum = 2 us / 16 = 125 ns. Prescaler = 80 MHz x 125 ns = 10. Segment allocation for 87.5% sample point: Sync_Seg = 1 TQ, Prop_Seg = 5 TQ, Phase_Seg1 = 8 TQ, Phase_Seg2 = 2 TQ. Sample point = (1 + 5 + 8) / 16 = 87.5%. SJW (Synchronization Jump Width) = min(Phase_Seg1, Phase_Seg2, 4) = 2 TQ, allowing resynchronization of +/-250 ns per bit. This configuration supports networks up to 100 meters with 5 ns/m propagation delay.
Practical Tips
- ✓Per ISO 11898-2, use 87.5% sample point for networks under 40 meters, reduce to 75% for networks 40-500 meters to accommodate propagation delay
- ✓Set SJW (Synchronization Jump Width) to the maximum allowed value (typically 1-4 TQ) to tolerate oscillator drift up to 1.58% per Bosch CAN specification
- ✓For CAN FD at 2 Mbps data phase, use transceiver propagation delay <150 ns (TJA1042 family) and keep stub lengths under 30 cm
Common Mistakes
- ✗Using mismatched bit timing between nodes - even 1 TQ difference causes sample point mismatch, increasing error frames by 10-50x on bus lengths >20 meters
- ✗Setting sample point above 90%, which violates ISO 11898-1 and causes 5-15% error rate on multi-node networks due to insufficient Phase_Seg2
- ✗Neglecting oscillator tolerance - ceramic resonators (0.5% accuracy) fail at cable lengths >50 meters while crystals (20 ppm) support the full 1 km range
Frequently Asked Questions
Shop Components
As an Amazon Associate we earn from qualifying purchases.
Related Calculators
Comms
SPI Timing
Calculate SPI bus timing parameters including bit period, frame time, maximum clock frequency limited by trace capacitance, and signal slew rate
Comms
UART Baud Rate
Calculate UART frame timing, throughput, and USART BRR register divisor from baud rate, data format, and MCU clock frequency. Identify baud rate error for reliable serial communication.
Comms
I2C Pull-Up
Calculate I2C pull-up resistor values for Standard (100 kHz), Fast (400 kHz), and Fast-Plus (1 MHz) modes. Derives minimum, maximum, and recommended resistance from supply voltage and bus capacitance per NXP UM10204.
Comms
Clock Jitter
Calculate clock tree timing budget for FPGA and SoC designs. Enter reference oscillator jitter, PLL noise floor, buffer stages, and target clock frequency to compute setup margin.