Phase Noise to Jitter Converter
Convert oscillator phase noise (dBc/Hz) to RMS jitter in ps and ADC SNR limit. Integrate over offset frequency range for clock design. Free, instant results.
Formula
How It Works
The Phase Noise to Jitter Calculator converts oscillator phase noise (dBc/Hz) to time-domain jitter (ps RMS) — essential for clock source selection, high-speed serial link design, and radar system development. Clock IC designers, SERDES engineers, and RF system architects use this to verify timing margins and select oscillators. Per IEEE 1139-2008, phase noise L(f) at offset f from carrier relates to jitter via integration: sigma_rms = (1/(2*pi*fc)) sqrt(2 integral[L(f)df]) from f1 to f2. A -100 dBc/Hz oscillator at 100 MHz with integration from 12 kHz to 20 MHz yields approximately 0.5 ps RMS jitter. Per Egan "Phase-Lock Basics" (2nd ed.), jitter directly impacts bit error rate: 0.1 UI jitter at 10 Gbps (10 ps) causes BER floor of 1e-12. Modern XO/TCXO oscillators achieve -110 to -150 dBc/Hz at 10 kHz offset, translating to sub-picosecond jitter.
Worked Example
Select oscillator for 10 Gbps SERDES requiring < 1 ps RMS jitter integrated 12 kHz to 20 MHz. Step 1: UI = 100 ps at 10 Gbps. Per IEEE 802.3, jitter budget = 0.15 UI = 15 ps total. Step 2: Clock source allocation = 30% = 4.5 ps. Step 3: Convert to phase noise requirement. For 100 MHz clock: -100 dBc/Hz flat yields ~0.8 ps. -110 dBc/Hz yields ~0.25 ps. Step 4: Select oscillator with L(10kHz) < -105 dBc/Hz. Step 5: Verify: SiTime SiT9121 specifies -115 dBc/Hz at 10 kHz, yielding 0.15 ps RMS — 30x margin. Per Maxim AN-3359, this approach ensures robust 10G link operation.
Practical Tips
- ✓Per IEEE 1139-2008, always specify integration bandwidth when reporting jitter — 12 kHz to 20 MHz is industry standard for SERDES
- ✓Close-in phase noise (< 1 kHz offset) dominates jitter for narrowband PLLs; far-from-carrier dominates for wideband systems
- ✓Use spectrum analyzer with cross-correlation for < -140 dBc/Hz measurements per Keysight AN 1316
- ✓Budget 3 dB margin below phase noise spec to account for temperature variation per SiTime application notes
Common Mistakes
- ✗Assuming linear phase noise to jitter relationship — integration is required; flat -100 dBc/Hz across decade yields different jitter than -100 at center
- ✗Neglecting integration bandwidth — 1 kHz to 100 MHz integration yields 10x higher jitter than 12 kHz to 20 MHz
- ✗Using single-point phase noise — must integrate across full PLL bandwidth or SERDES CDR bandwidth per IEEE 802.3
Frequently Asked Questions
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