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Time Unit Converter

Convert time between seconds, milliseconds, microseconds, nanoseconds, picoseconds, and femtoseconds for digital and RF applications.

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Formula

1 s = 10³ ms = 10⁶ μs = 10⁹ ns = 10¹² ps = 10¹⁵ fs

How It Works

Time in electronics spans an enormous range: femtoseconds (10⁻¹⁵ s) for optical pulses and laser physics, picoseconds (ps) for digital timing margins and RF propagation delays, nanoseconds (ns) for logic gate switching and microcontroller clock cycles, microseconds (μs) for interrupt latency and ADC conversion time, and milliseconds (ms) for audio, PWM, and human-interface events.

Worked Example

A 100 MHz clock has a period of 10 ns: 10 ns = 10,000 ps = 0.01 μs = 0.00001 ms = 0.00000001 s. A Wi-Fi packet guard interval of 800 ns: 800 ns = 0.8 μs = 800,000 ps = 0.0008 ms.

Practical Tips

  • ✓Digital signal propagation on a PCB is approximately 150–170 ps/inch (6–7 ps/mm). Match trace lengths for differential pairs to within a few ps.
  • ✓Oscilloscope timebase selection: use 10 ns/div for GHz signals, 100 ns/div for 100 MHz signals, 1 μs/div for MCU timing, and 1 ms/div for audio and PWM waveforms.
  • ✓RTOS task scheduling is typically in the 1–10 ms range; ISR latency is typically 100 ns to a few μs depending on processor and priority.

Common Mistakes

  • ✗Confusing ns (nanosecond) with μs (microsecond) — 1 μs = 1000 ns; a 10 ns propagation delay is much faster than 10 μs.
  • ✗Misinterpreting datasheet timing diagrams where setup time, hold time, and propagation delay are mixed in ns and ps on the same diagram.
  • ✗Using floating-point math for timing in embedded firmware without considering rounding errors — use integer timer counts where possible.

Frequently Asked Questions

Propagation delay is the time for a signal to travel from input to output through a gate, trace, or cable. Logic gates have propagation delays of 0.1–10 ns; longer PCB traces add ~170 ps/inch.
A 48 MHz MCU has a clock period of ~20.8 ns. Hardware timers can resolve time to one clock cycle; software latency adds μs-range uncertainty unless you use hardware capture.
At 5 GHz, one clock cycle is 200 ps. Timing jitter of even 1 ps adds significant phase noise. PCB trace mismatch of 1 mm introduces ~7 ps of skew, enough to affect multi-GHz differential signals.
Jitter is the variation in a signal's timing relative to its ideal position, measured in ps or ns RMS or peak-to-peak. Excessive jitter in clocks causes ADC SNR degradation and serial link bit errors.

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