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EMC

Decoupling Capacitor EMC Selection

Calculate decoupling capacitor impedance at frequency and self-resonant frequency for EMC power supply decoupling.

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Formula

Xc = 1/(2πfC), f_SRF = 1/(2π√LC)

C— Capacitance (F)
L— Package inductance (varies by package) (H)

How It Works

Decoupling capacitors suppress power-supply noise by providing a low-impedance path for high-frequency currents close to the IC. The capacitive reactance at frequency f is Xc = 1/(2πfC). In practice, every capacitor has an equivalent series resistance (ESR) and equivalent series inductance (ESL, typically 0.5–2 nH for SMD packages). The total impedance is |Z| = √(Xc² + ESR²) below self-resonance, and the self-resonant frequency is f_SRF = 1/(2π√(L_pkg × C)) where L_pkg ≈ 1 nH for a 0402 package. Above f_SRF the capacitor behaves inductively and loses its decoupling effectiveness. For EMC, choose capacitor values so f_SRF falls near the switching frequency or clock harmonic to be suppressed. Multiple capacitors in parallel extend the low-impedance bandwidth.

Worked Example

Problem
A 100 nF capacitor with ESR = 0.05 Ω needs to decouple a 100 kHz switching supply. What is its impedance at 100 kHz, and what is its self-resonant frequency assuming 1 nH package inductance?
Solution
1. Xc at 100 kHz: C = 100 nF = 100×10⁻⁹ F; Xc = 1/(2π × 100,000 × 100×10⁻⁹) = 15.9 mΩ 2. Total impedance: |Z| = √(0.0159² + 0.05²) = 52.5 mΩ 3. SRF: f_SRF = 1/(2π√(1×10⁻⁹ × 100×10⁻⁹)) = 1/(2π × 10⁻⁸) = 15.9 MHz Result: At 100 kHz the capacitor is well below SRF and provides good decoupling. At 15.9 MHz it resonates; above this frequency a smaller capacitor (e.g. 1 nF) should be added in parallel.

Practical Tips

  • ✓Use multiple capacitor values in parallel (e.g. 10 μF + 100 nF + 1 nF) to cover a wide frequency range from kHz to hundreds of MHz.
  • ✓Place 0402 or 0201 capacitors on the same layer directly under IC power pins for minimum package inductance.
  • ✓For multi-layer PCBs, use power and ground plane pairs as distributed capacitance — they provide effective decoupling above 100 MHz where discrete capacitors become inductive.

Common Mistakes

  • ✗Using only a single large bulk capacitor — above its SRF it becomes inductive. A 10 μF tantalum has SRF around 1 MHz; add a parallel 100 nF ceramic for higher frequencies.
  • ✗Ignoring package inductance — a 0805 capacitor has ~2 nH, a 0402 ~0.7 nH; this directly limits the highest frequency decoupled.
  • ✗Placing the capacitor far from the IC power pin — every mm of trace adds inductance (≈1 nH/mm), raising effective ESL and degrading decoupling above a few MHz.

Frequently Asked Questions

A common rule is 100 nF per power pin for frequencies up to ~10 MHz (check SRF), plus one 10 μF bulk capacitor per supply rail per IC cluster. For ICs with fast edges (DDR, GHz clocks), also add 10 nF or 1 nF per power pin.
Smaller capacitance values have proportionally smaller ESL impact on SRF. A 10 nF 0402 capacitor has SRF ≈ 50 MHz versus ≈15 MHz for 100 nF. For suppressing clock harmonics at 100+ MHz, 10 nF can be more effective.
At frequencies well below SRF, Xc dominates and ESR is negligible. Near SRF, ESR limits the minimum impedance (impedance = ESR at resonance). For EMC, lower ESR is generally better, which is why X5R/X7R ceramic capacitors are preferred over tantalum for high-frequency decoupling.

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