Skip to content
RFrftools.io
EMC

Decoupling Capacitor EMC Selection

Calculate decoupling capacitor impedance, reactance, and self-resonant frequency. Select bypass caps by package for EMC power integrity.

Loading calculator...

Formula

Xc=1/(2πfC),fSRF=1/(2π√LC)Xc = 1/(2πfC), f_SRF = 1/(2π√LC)
C— Capacitance (F)
L— Package inductance (varies by package) (H)

How It Works

The Decoupling Capacitor EMC Calculator determines optimal values and placement for conducted emissions suppression — essential for CISPR 32 compliance, FPGA PDN design, and switching regulator noise reduction. EMC engineers use this to achieve 20-40 dB noise attenuation at specific frequencies while avoiding resonances that can worsen emissions.

Per Henry Ott's 'EMC Engineering' and Murata application notes, capacitor impedance Z = sqrt((1/(2 x pi x f x C))^2 + ESR^2) below self-resonant frequency (SRF), and Z = 2 x pi x f x ESL above SRF. A 100 nF MLCC with 0.7 nH ESL (0402 package) resonates at f_SRF = 1/(2 x pi x sqrt(0.7e-9 x 100e-9)) = 19 MHz. Above 19 MHz, the capacitor becomes inductive and loses decoupling effectiveness.

Per IPC-2152 and Smith's 'High-Speed Digital System Design,' multiple capacitor values in parallel create overlapping low-impedance bands: 10 uF covers DC-1 MHz; 100 nF covers 1-30 MHz; 10 nF covers 30-100 MHz; 1 nF covers 100-300 MHz. Each value handles frequencies around its SRF where impedance equals ESR (typically 10-50 mohm for MLCCs).

Placement is critical per Johnson/Graham: every mm of trace between capacitor and IC power pin adds approximately 1 nH inductance, shifting effective SRF downward and degrading high-frequency decoupling. A capacitor 10mm from IC has 10 nH added ESL, reducing effectiveness above 5 MHz by 20 dB versus direct connection.

Worked Example

Problem: Design decoupling for 200 MHz FPGA showing conducted emissions 12 dB above CISPR 32 limit at 180 MHz. Current PDN has only 10 uF bulk capacitors.

Solution per Ott:

  1. Problem frequency: 180 MHz — above SRF of 10 uF (approximately 500 kHz) and 100 nF (approximately 19 MHz)
  2. Required attenuation: 12 dB + 6 dB margin = 18 dB at 180 MHz
  3. Capacitor for 180 MHz: need SRF near 180 MHz; C = 1/(4 x pi^2 x f^2 x L) = 1/(4 x pi^2 x (180e6)^2 x 0.7e-9) = 1.1 nF
  4. Select 1 nF 0402 MLCC (SRF approximately 190 MHz, ESR approximately 30 mohm)
  5. Impedance at SRF: Z = ESR = 30 mohm
  6. Decoupling effectiveness: if PDN impedance was 3 ohm at 180 MHz, adding capacitors reduces to 30 mohm — improvement = 20 x log10(3/0.03) = 40 dB
  7. Use 4x 1 nF capacitors in parallel: Z = 30/4 = 7.5 mohm
Placement: 1 nF capacitors within 2mm of FPGA power pins on same layer (no via in decoupling path). Add on all four sides of BGA.

Practical Tips

  • ✓Use '1-2-4 rule' for FPGA decoupling — per Intel/Xilinx: 1x 10 uF bulk per rail, 2x 100 nF per power pin cluster, 4x 10 nF distributed across die area. Provides flat impedance from 100 kHz to 200 MHz.
  • ✓Place capacitors on same layer as IC power pins — per Smith, via in decoupling path adds 1-2 nH inductance. Back-side capacitors under BGA with via-in-pad achieve near-zero added inductance.
  • ✓Measure PDN impedance with VNA to identify resonances — per Sandler, simulation accuracy is +/-30%; actual measurement reveals anti-resonances between plane and capacitors that cause impedance peaks at specific frequencies.

Common Mistakes

  • ✗Using only large capacitors (10 uF) for high-frequency noise — per Ott, 10 uF SRF is approximately 500 kHz; above 1 MHz the capacitor is inductive with increasing impedance. Emissions at 100+ MHz require 1-10 nF capacitors with higher SRF.
  • ✗Ignoring package inductance — per Murata, 0805 package has 1.2 nH ESL versus 0.7 nH for 0402. Larger packages have lower SRF: 100 nF in 0805 resonates at 14 MHz versus 19 MHz in 0402. Use smallest package for highest frequency effectiveness.
  • ✗Placing capacitors far from IC — per Johnson/Graham, 10mm trace adds 10 nH, equivalent to changing from 0402 to large through-hole capacitor. Route power and ground directly under capacitor with via to plane or use via-in-pad for minimum inductance.

Frequently Asked Questions

Per Murata guidelines: (1) 10-100 uF bulk per supply rail (DC-1 MHz); (2) 100 nF per power pin (1-30 MHz); (3) 10 nF if switching >50 MHz (30-100 MHz); (4) 1 nF if >200 MHz clocks (100-300 MHz). For microcontrollers: 100 nF per power pin is usually sufficient. For FPGAs: full range needed with quantities per Intel/Xilinx design guide.
Per Ott: 10 nF has higher SRF (approximately 60 MHz in 0402) than 100 nF (approximately 19 MHz). For suppressing noise at 50-150 MHz, 10 nF is more effective because it's still capacitive in that range. Use 100 nF for DC-30 MHz filtering; use 10 nF for 30-100 MHz; use 1 nF for 100-300 MHz. Multiple values cover the full spectrum.
Yes at SRF — per Murata, capacitor impedance equals ESR at self-resonant frequency. X5R/X7R ceramics have ESR of 10-50 mohm; tantalum has 50-500 mohm. At SRF, low-ESR ceramic provides 10-20 dB better decoupling than tantalum. Above and below SRF, ESR matters less. Use X5R/X7R MLCC for EMC decoupling; tantalum only for bulk storage.
Per Intel/Xilinx guidelines: simple MCUs need 1 capacitor per power pin; complex FPGAs need 50-200 capacitors total depending on power consumption and switching speed. Rule of thumb: 1 capacitor per mA of switching current at the frequency of concern. For a 100 MHz FPGA drawing 2A core current: approximately 20-40 high-frequency decoupling capacitors minimum.
Yes — per Smith, anti-resonance between capacitor ESL and plane capacitance can create impedance peaks 10-100x higher than either alone at specific frequencies. If anti-resonance coincides with a noise harmonic, emissions at that frequency worsen. Solution: use multiple capacitor values so resonances overlap; add damping with series RC snubber if specific anti-resonance is problematic.

Shop Components

As an Amazon Associate we earn from qualifying purchases.

Copper Foil Tape

Copper foil tape for EMI shielding and grounding

Amazon →

Ferrite Bead Kit

SMD ferrite bead assortment for suppressing high-frequency noise

Amazon →

Related Calculators

EMC

LC EMI Filter

Design LC EMI filters for conducted emissions compliance. Calculate inductance, capacitance, cutoff frequency, and attenuation for CISPR 22/32 and FCC Part 15. Free, instant results.

EMC

CMC Impedance

Calculate common mode choke impedance, insertion loss, and Q factor at any frequency. Design EMC filters for CISPR 25 conducted emissions compliance.

EMC

Conducted EMI Filter

Design an LC filter for CISPR 22/FCC conducted emissions compliance. Calculate required inductor and capacitor values for target attenuation.

EMC

RF Shielding

Calculate electromagnetic shielding effectiveness, absorption loss, reflection loss, and skin depth. Evaluate enclosure materials per MIL-STD-285.