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LDO Dropout Voltage Calculator

Calculate LDO minimum input voltage from dropout specification, determine power dissipation, and estimate efficiency at a given supply voltage.

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Formula

η=VoutVin×100%\eta = \frac{V_{out}}{V_{in}} \times 100\%
Vout— Regulated output voltage (V)
Vdropout— LDO dropout voltage (V)
Iload— Load current (A)
Rds(on)— Pass MOSFET on-resistance (Ω)

How It Works

The voltage regulator dropout calculator determines minimum input voltage and efficiency loss for LDO regulators — essential for battery-powered devices, post-regulator stages, and noise-sensitive analog circuits. Power management engineers, portable device designers, and mixed-signal architects use this tool to maximize battery utilization while ensuring stable output voltage. According to TI application note SLVA079, dropout voltage represents the minimum Vin - Vout differential for regulation; below this threshold, output tracks input with degraded PSRR. Modern ultra-low dropout regulators achieve 50-150 mV at rated current using PMOS pass transistors (Rds(on) = Vdropout/Iload). Per Analog Devices' LDO selection guide, dropout increases approximately linearly with load current: a 150 mV dropout at 500 mA device exhibits 300 mV at 1 A. For lithium-ion battery applications (4.2 V to 3.0 V discharge range), an LDO with 200 mV dropout powering 3.3 V load operates in regulation until 3.5 V battery voltage — capturing 75% of total battery energy versus only 60% with a 500 mV dropout regulator.

Worked Example

Select an LDO for a BLE sensor operating from single-cell Li-ion (4.2-3.0 V) to 3.3 V/100 mA output. Requirements: operate until battery reaches 3.4 V (95% capacity utilization), <5 µA quiescent current, PSRR >60 dB at 1 kHz. Step 1: Calculate maximum dropout — Vdropout_max = 3.4 - 3.3 = 100 mV at 100 mA. Step 2: Screen candidates — TI TPS7A02 (25 mV @ 100 mA, 25 nA Iq), Analog Devices ADP160 (90 mV @ 100 mA, 560 nA Iq), Torex XC6220 (100 mV @ 100 mA, 8 µA Iq). Step 3: Verify thermal — Pdiss_max = (4.2 - 3.3) × 0.1 = 90 mW in SOT-23 (θJA = 180°C/W): ΔT = 16°C — acceptable. Step 4: Evaluate PSRR — TPS7A02: 60 dB at 1 kHz, 40 dB at 100 kHz. ADP160: 70 dB at 1 kHz. Step 5: Select — TPS7A02 for lowest Iq (25 nA) in always-on applications, ADP160 for best PSRR in RF/analog applications.

Practical Tips

  • ✓Per Analog Devices 'LDO Basics' application note, use PMOS-based LDOs for lowest dropout (50-200 mV) versus NPN-based (500 mV-2 V); NMOS LDOs require charge pump but achieve intermediate dropout (200-400 mV)
  • ✓Add 100 mV margin to calculated minimum input voltage for manufacturing tolerance, temperature variation, and transient headroom — a 100 mV dropout device needs 200 mV nominal headroom
  • ✓For critical battery applications, select LDOs with reverse current blocking to prevent battery drain through the LDO when Vout > Vin during shutdown

Common Mistakes

  • ✗Ignoring dropout variation with load current — datasheet typically specifies dropout at one current (e.g., 150 mV at 500 mA), but at 1 A it may reach 350 mV due to pass transistor Rds(on) × current
  • ✗Using typical dropout instead of maximum — per TI specifications, typical to maximum dropout ratio is 1:1.5 to 1:2 across temperature range; design to maximum value
  • ✗Neglecting transient dropout — load current step from 10 mA to 500 mA causes 50-100 mV additional dropout during 10-50 µs settling period due to control loop bandwidth

Frequently Asked Questions

Per TI SLVA118, dropout voltage is the minimum Vin - Vout differential to maintain regulation within specified accuracy (typically 1-2%). Below dropout, output follows input minus the pass transistor's minimum saturation voltage. For PMOS LDOs, dropout = Iload × Rds(on); for NPN LDOs, dropout = Vce(sat) + sense resistor drop (typically 0.5-1 V minimum).
Low dropout maximizes usable battery capacity and reduces heat dissipation. Per Battery University, a 100 mV dropout LDO extracts 8% more energy from a Li-ion cell than a 300 mV dropout regulator. In high-current applications (>1 A), the 200 mV difference represents 200+ mW of heat — potentially eliminating the need for heatsinking.
Vin_min = Vout + Vdropout_max + Vmargin. Example: 3.3 V output, 150 mV max dropout, 100 mV margin → Vin_min = 3.55 V. For AC-DC applications, include rectifier voltage (0.7 V for silicon, 0.3 V for Schottky) and ripple amplitude in Vin_min calculation. Per TI design guide, post-rectifier capacitor must maintain Vin > Vin_min at ripple valley.
LDO efficiency = Vout/Vin × 100%, limited to theoretical maximum of Vout/(Vout + Vdropout). A 3.3 V output with 200 mV dropout: η_max = 3.3/3.5 = 94.3%. At Vin = 5 V: η = 3.3/5 = 66%. LDOs are efficient only when Vin ≈ Vout; for Vin > 1.5×Vout, switching regulators achieve 90%+ efficiency versus LDO's 50-70%.
Per Maxim Integrated application note AN-883: Standard LDO (NPN Darlington): 1-2 V dropout. Low dropout (NMOS): 300-500 mV dropout, requires charge pump for gate drive. Ultra-low dropout (PMOS): 50-200 mV dropout, no charge pump needed. Modern ultra-LDOs (TI TPS7A02, ADP160) achieve 25-100 mV at full current with <1 µA quiescent current.

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