PLL Loop Filter Designer
Design a type-2 second-order PLL passive loop filter. Calculates time constants, capacitor and resistor values for target loop bandwidth and phase margin.
Formula
How It Works
The PLL Loop Filter Calculator computes component values for Type-2 phase-locked loop filters — essential for frequency synthesizer design, clock recovery circuits, and communication system development. IC designers, RF engineers, and embedded developers use this to achieve target loop bandwidth and phase margin. Per Best 'Phase-Locked Loops: Design, Simulation, and Applications' (6th ed., McGraw-Hill) and Banerjee 'PLL Performance, Simulation, and Design' (5th ed.), Type-2 PLL uses charge pump with passive RC filter providing second-order response. PLL noise specifications relevant to communication systems follow ITU-R SM.1538 and IEEE Standard 1139-2008 (IEEE Standard Definitions of Physical Quantities for Fundamental Frequency and Time Metrology — Random Instabilities). Loop bandwidth omega_c determines lock time (t_lock ~ 2*pi/omega_c) and phase noise filtering — wider bandwidth tracks input faster but passes more reference noise. Phase margin phi_m controls overshoot: 45 deg yields 23% overshoot, 65 deg yields 5%. Per Banerjee "PLL Performance, Simulation, and Design" (5th ed.), optimal phi_m = 48-55 deg balances speed and stability. Component equations: C1 = Icp*Kvco/(omega_c^2*N), R1 = tan(phi_m)*omega_c*C1, C2 = C1/10 for 10x pole spacing.
Worked Example
Design loop filter for 2.4 GHz frequency synthesizer with 100 kHz bandwidth, 50 deg phase margin. Parameters: Icp = 1 mA, Kvco = 50 MHz/V, N = 48. Step 1: omega_c = 2*pi*100e3 = 628 krad/s. Step 2: C1 = 1e-3 50e6 / (628e3^2 48) = 2.64 nF. Select 2.7 nF. Step 3: R1 = tan(50deg) 628e3 2.7e-9 = 2.02 kohm. Select 2.0 kohm. Step 4: C2 = 2.7 nF / 10 = 270 pF. Select 270 pF. Step 5: Verify: zero frequency = 1/(2*pi*R1*C1) = 29.5 kHz. Pole frequency = 1/(2*pi*R1*C2) = 295 kHz. Per ADIsimPLL simulation, this achieves 105 kHz actual bandwidth with 48 deg margin — meets Analog Devices ADF4351 reference design.
Practical Tips
- ✓Per Best, target 48-55 deg phase margin for optimal settling time vs. stability tradeoff
- ✓Use C2 = C1/10 minimum for adequate pole spacing — tighter ratio increases reference spur rejection per Banerjee
- ✓Verify loop stability with Bode plot simulation — 6 dB gain margin minimum per control theory standards
- ✓For low phase noise, minimize R1: thermal noise contribution = 4kTR1*Kvco^2/(omega_c*N)^2 per Egan
Common Mistakes
- ✗Neglecting phase margin impact on settling — 30 deg margin causes 50% overshoot and 5x longer lock time vs. 55 deg
- ✗Incorrectly calculating time constants — tau1 = R1*C1, tau2 = R1*C1*C2/(C1+C2), NOT just R1*C2
- ✗Overlooking VCO gain variation — Kvco can vary 2:1 over tuning range, degrading phase margin by 20 deg per Texas Instruments SCAA030
Frequently Asked Questions
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