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Time Unit Converter

Convert time between seconds, milliseconds, microseconds, nanoseconds, picoseconds, and femtoseconds for digital and RF applications.

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Formula

1s=103ms=106mus=109ns=1012ps=1015fs1 s = 10³ ms = 10⁶ mu s = 10⁹ ns = 10¹² ps = 10¹⁵ fs

How It Works

This calculator converts between seconds, milliseconds, microseconds, nanoseconds, picoseconds, and femtoseconds for electronics engineers, embedded developers, and RF designers working with timing-critical systems. Per SI Brochure (BIPM), the second is defined by cesium-133 hyperfine transition: exactly 9,192,631,770 periods. Electronics timing spans 18 orders of magnitude: femtoseconds (10^-15 s) for optical pulses, picoseconds for high-speed serial (PCIe 5.0 UI = 31.25 ps), nanoseconds for DRAM timing (tCL = 14-22 ns), microseconds for ADC conversion (SAR ADC: 1-10 us), and milliseconds for human interface (response time < 100 ms per ISO 9241). Signal propagation on PCB is 6.67 ps/mm in FR-4, making timing margins critical at GHz frequencies.

Worked Example

Problem

A DDR4-3200 memory interface has a data eye of 312.5 ps (UI). Calculate timing margins accounting for 50 ps jitter, 30 ps setup time, and 6-inch trace length mismatch.

Solution
  1. Unit interval: 312.5 ps = 0.3125 ns = 0.0003125 us
  2. Trace delay: 6 inches × 170 ps/inch (FR-4) = 1020 ps = 1.02 ns
  3. Available margin: 312.5 - 50 (jitter) - 30 (setup) = 232.5 ps
  4. Trace mismatch budget: must be < 232.5 ps = 232.5/170 = 1.37 inches max skew
  5. Actual 6-inch mismatch: 1020 ps >> 232.5 ps budget - FAIL
  6. Required matching: 232.5 ps / 170 ps/inch = 1.37 inches, so traces must match to < 1.4 inches

Practical Tips

  • ✓PCB propagation delay per IPC-2141: microstrip on FR-4 = 6.0-6.8 ps/mm (varies with trace geometry), stripline = 7.0 ps/mm. Use actual stackup parameters for timing closure
  • ✓Oscilloscope selection: 10 ns/div for GHz signals, 100 ns/div for 100 MHz, 1 us/div for MCU timing, 1 ms/div for audio/PWM. Bandwidth should be > 5x signal frequency for < 3% amplitude error
  • ✓JEDEC memory timing: DDR4-3200 has tCK = 625 ps (clock period), tRCD = 13.75 ns (row-to-column delay), tRP = 13.75 ns (precharge). Convert all to same unit before timing analysis

Common Mistakes

  • ✗Confusing ns (10^-9 s) with us (10^-6 s) - they differ by 1000x. A 10 ns propagation delay is 1000x faster than 10 us. DDR timing is ns, ADC conversion is us
  • ✗Ignoring propagation delay in high-speed PCB design - signals travel ~6 ps/mm on FR-4. A 100 mm trace adds 600 ps delay, exceeding timing margin for signals > 500 MHz
  • ✗Using floating-point for firmware timing without considering precision - at 100 MHz (10 ns period), float32 only provides 24-bit mantissa = 6 us resolution, inadequate for ns-level timing

Frequently Asked Questions

Propagation delay (tpd) is time for signal to travel from input to output. Per semiconductor datasheets: CMOS gate tpd = 0.1-10 ns depending on technology node (14 nm CMOS: ~10 ps, discrete 74HC: ~10 ns). PCB trace: ~170 ps/inch in FR-4 (6.7 ps/mm). Coax cable: 1.0-1.5 ns/foot depending on velocity factor.
Timer resolution = 1/f_clock. At 48 MHz: 20.83 ns/tick. At 200 MHz: 5 ns/tick. Hardware capture provides single-cycle resolution. Software polling adds 3-10 cycles overhead = 60-200 ns at 48 MHz. For sub-ns timing, use dedicated timer ICs (TDC) with 10-100 ps resolution per datasheet specs.
At 5 GHz: period = 200 ps, so 10 ps jitter = 5% of cycle = significant phase noise. Per IEEE 802.11ax: EVM requires < 2% = 4 ps timing precision. PCB trace mismatch of 1 mm = 6.7 ps skew. DDR5 at 4800 MT/s has 104 ps UI - trace matching must be within ~20 ps (3 mm) for reliable operation.
Jitter is timing variation from ideal position, specified as RMS (1-sigma) or peak-to-peak per JEDEC JESD65C. Sources: PLL (1-10 ps RMS), clock buffer (0.5-2 ps), power supply (1-5 ps per mV ripple). Impact: ADC SNR degrades as SNR_jitter = -20×log10(2×pi×f_in×t_jitter). At 100 MHz input with 1 ps jitter: SNR_jitter = 64 dB limit.

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