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RFrftools.io

PCB Stack-Up Builder

Build your board layer by layer, then compute controlled impedance for any trace — microstrip, stripline, differential pairs, or coplanar waveguide.

⠇⠇SMSoldermask (top)
mm
⠇⠇CuL1 — Signal
⠇⠇PPPrepreg
mm
⠇⠇CuL2 — Ground
⠇⠇CoreCore — FR4
mm
⠇⠇CuL3 — Power
⠇⠇PPPrepreg
mm
⠇⠇CuL4 — Signal
⠇⠇SMSoldermask (bottom)
mm
1.555 mm0.0250Soldermask (top)1 ozL1 — Signal0.100Prepreg0.5 ozL2 — Ground1.200Core — FR40.5 ozL3 — Power0.100Prepreg1 ozL4 — Signal0.0250Soldermask (bottom)

Trace Specification

Results

Configure trace parameters and run the calculation to see results.

How Controlled Impedance Works

A PCB stack-up defines every layer of your board — copper, dielectric, and soldermask — and controls the electrical environment that signals travel through. When a high-speed or RF signal propagates along a trace, it behaves as a transmission line: it has a characteristic impedance Z₀ determined entirely by the geometry and material properties around it. The four key parameters that set Z₀ are: • Trace width (W) — wider traces lower impedance • Dielectric height (H) — the distance to the nearest reference plane; larger H raises impedance • Conductor thickness (T) — thicker copper slightly lowers impedance via the effective width correction • Relative permittivity (εᵣ) — higher εᵣ lowers both Z₀ and propagation velocity For a microstrip (outer layer, trace on top), the field exists partly in the dielectric and partly in the air above, giving an effective εᵣ between 1 and the substrate value. For a stripline (inner layer, fully buried), the field is entirely within the dielectric, so εᵣ_eff equals the bulk value and propagation delay is higher. FR4's εᵣ is not a constant — it ranges from ~4.6 at 1 MHz to ~4.2 at 5 GHz due to moisture absorption and the Djordjevic-Sarkar dispersion model. Rogers materials like RO4350B are specified at 3.48 ±0.05 from 1–10 GHz, which is why they are preferred above 2 GHz. Propagation delay (t_pd) follows: t_pd = √εᵣ_eff / c₀ ≈ 6.2 ps/mm for standard FR4 microstrip at 50 Ω. For DDR4 at 1.6 GT/s, a 10 mm length mismatch causes ~62 ps skew — significant against the ~312 ps UI. Controlled impedance is specified on the fabrication drawing as a note (e.g. "50 Ω ±10% on L1/L4 per IPC-2141A") and the fab house measures it on a coupon. JLC standard 4-layer achieves ±10%; advanced processes reach ±5%.

Worked Example

Problem
You are designing a 2.4 GHz WiFi front-end on a JLC standard 4-layer board (1.6 mm total, FR4, 1 oz outer copper). The RF trace on L1 must be 50 Ω. What trace width do you need?
Solution
The JLC standard 4-layer uses a 0.1 mm prepreg between L1 and L2. L2 is the ground reference. Copper weight is 1 oz (34.8 µm).

For microstrip on FR4 with H = 0.100 mm, T = 0.035 mm, εᵣ = 4.5, the Hammerstad-Jensen formula gives Z₀ ≈ 44 Ω at W = 0.200 mm. Using the Solve function with Target Z₀ = 50 Ω → solved width ≈ 0.158 mm (εᵣ_eff ≈ 3.39).

Propagation delay: t_pd = √3.39 / 299.8 ≈ 6.13 ps/mm. A 25 mm antenna feed trace adds ~153 ps — negligible for most 2.4 GHz matching network tolerances.

Fab note: “L1/L4 microstrip: W = 0.16 mm, Z₀ = 50 Ω ±10%, per IPC-2141A. Route over solid L2/L3 reference planes.”

Practical Tips

  • ✓Always confirm your fab's actual stack-up before designing. JLC, PCBWay, and OSHPark each publish their exact dielectric thicknesses and εᵣ values — do not assume generic FR4 numbers.
  • ✓Use 1 oz copper on signal layers for tighter impedance control. 2 oz increases effective trace width and shifts Z₀ by 3–5 Ω for a given layout width.
  • ✓Route impedance-controlled traces over continuous reference planes. Any slot, cutout, or via antipads in the reference plane directly below the trace disturbs the return current path and degrades the impedance by 10–30%.
  • ✓Add a 3 mil clearance around impedance-controlled traces in the copper pour keepout. A neighboring copper pour at the same potential as the reference plane can act as a ground shield — useful for CPWG.
  • ✓For differential pairs (USB, PCIe, HDMI, Ethernet), maintain the trace spacing constant through the entire route — including at vias and connectors. Even a short segment of wider spacing increases Zdiff and degrades return loss.
  • ✓At GHz frequencies, use FR4-HF, Isola I-Speed, or Rogers materials. Standard FR4 loss tangent (tan δ ≈ 0.020) causes 0.5–1.5 dB/cm attenuation at 5 GHz — significant for longer traces.
  • ✓Always include a controlled impedance note and impedance coupon in your Gerber package. Without a coupon, the fab cannot verify compliance, and you have no traceability if failures occur.
  • ✓Check the soldermask effect: a 25 µm soldermask layer over a microstrip lowers Z₀ by ~1–2 Ω. Use Embedded Microstrip mode in this tool to model it accurately.

Common Mistakes

  • ✗Using the wrong εᵣ value. FR4 is typically specified at 1 MHz (εᵣ ≈ 4.6) but you should use the frequency-dependent value. At 1 GHz it is ~4.4; at 5 GHz it is ~4.2. Using 4.5 at 5 GHz adds ~3% Z₀ error.
  • ✗Placing a controlled impedance trace on an inner layer and using Symmetric Stripline when the geometry is actually asymmetric. JLC 4-layer has 0.1 mm prepreg above L2 and 1.2 mm core below — use Asymmetric Stripline for L2.
  • ✗Forgetting that copper thickness shifts impedance. Moving from 0.5 oz to 1 oz outer copper on a 50 Ω microstrip changes the solved width by ~15 µm — relevant when tight ±5% tolerance is required.
  • ✗Running impedance-controlled traces through via fields without stitching grounds. Each un-stitched gap in the reference plane introduces a local impedance discontinuity that reflects energy back toward the source.
  • ✗Assuming propagation delay is the same on all layers. An outer microstrip (εᵣ_eff ≈ 3.4) propagates at ~6.1 ps/mm while a symmetric stripline (εᵣ_eff = 4.5) propagates at ~7.1 ps/mm. Length matching between layers requires accounting for this ~14% difference.
  • ✗Specifying controlled impedance without a coupon. Without a test coupon on the panel, the fab cannot TDR-verify your impedance, and any impedance-related failures in production cannot be diagnosed.
  • ✗Changing the layer stack mid-design and forgetting to update impedance calculations. If you add a layer or change a core thickness, all previously-calculated trace widths are no longer valid.

Frequently Asked Questions

Controlled impedance means designing and manufacturing a PCB trace to have a specific characteristic impedance Z₀ — typically 50 Ω for RF/microwave or 100 Ω differential for digital interfaces. At low frequencies, signal integrity is dominated by resistance; at high frequencies (roughly above 100 MHz or when trace length exceeds 1/10 of the signal wavelength), the trace behaves as a transmission line. If the trace impedance does not match the source and load, part of the signal is reflected back, causing ringing, reduced eye opening, and degraded signal integrity.
Most standard PCB fabs (JLC, PCBWay, OSHPark) can achieve ±10% controlled impedance. Advanced processes or dedicated RF board fabs offer ±5%. For RF work at 2.4 GHz, ±10% is usually acceptable — a 50 Ω trace at ±10% gives 45–55 Ω, resulting in a worst-case VSWR of about 1.22:1 (return loss ~20 dB). For millimeter-wave or high-volume production, request ±5% and verify with TDR measurement coupons.
Microstrip is a trace on the outer layer of the PCB, with dielectric below and air (or soldermask) above. Because part of the field is in air (εᵣ = 1), the effective permittivity is lower and the impedance is higher for a given width. Stripline is a trace on an inner layer, fully surrounded by dielectric material. The entire field is in the dielectric, giving a higher effective εᵣ, slower propagation, and more attenuation. Stripline offers better isolation and shielding from external interference; microstrip is simpler to fabricate and diagnose.
CPWG places ground copper coplanar with the trace on both sides, in addition to the ground plane below. This combination allows tight impedance control with a thicker substrate (useful when you need the reference plane far away) and provides lateral shielding. It is commonly used in RF PCB designs where the ground reference plane is more than 0.3 mm away, or for transitions around connectors and chip pads where you need a well-defined ground reference close to the signal. The coplanar gap distance g is an additional tuning parameter alongside trace width.
Standard FR4 has εᵣ ≈ 4.5–4.7 at 1 MHz, falling to approximately 4.2–4.4 at 1 GHz and 4.0–4.2 at 5 GHz. This is modeled by the Djordjevic-Sarkar dispersion equation. The variation is caused by relaxation of the epoxy polymer dipoles at higher frequencies. This tool applies that dispersion model when you enter a frequency in the 'Frequency (GHz)' field — the displayed εᵣ values are frequency-corrected. For designs above 2 GHz, use measured datasheet values or choose low-loss laminates (Rogers, Isola I-Speed) with a tightly specified εᵣ.
Symmetric stripline has the trace centered exactly between two reference planes, with equal dielectric height above and below. The formula is simple and the impedance is the same whether you rotate the board. Asymmetric stripline has unequal heights above and below the trace. This is the common real-world case for inner layers — on a 4-layer board, L2 sits 0.1 mm below L1 (the prepreg) and 1.2 mm above L3 (the core), making it highly asymmetric. For asymmetric geometries with height ratios above 2:1, always select 'Asymmetric Stripline' — the symmetric formula overestimates Z₀ by 10–25% in such cases.
Propagation delay t_pd = √εᵣ_eff / c₀, where c₀ = 299.8 mm/ns. For a 50 Ω FR4 microstrip (εᵣ_eff ≈ 3.4), t_pd ≈ 6.1 ps/mm. For stripline (εᵣ_eff = 4.5), t_pd ≈ 7.1 ps/mm. DDR4 at 3200 MT/s has a 312 ps unit interval; PCIe Gen 3 requires skew below ±20 ps within a differential pair. A 10 mm trace length mismatch on FR4 microstrip introduces ~61 ps skew — enough to violate DDR4 timing margins. The 'Propagation delay' value in this tool is shown for the current geometry and can be directly compared to your interface specification.
The Hammerstad-Jensen closed-form formula for microstrip is accurate to ±1–2% for typical PCB geometries (0.1 ≤ W/H ≤ 10, T/H < 0.2). Stripline formulas are accurate to ±1.5%. Errors increase at extreme W/H ratios (very narrow or very wide traces), at transitions, or near via pads and copper pours. For designs where impedance tolerance is critical (±3% or tighter), complement these calculations with 2.5D or 3D EM simulation (e.g. HyperLynx, CST, or OpenEMS). For standard ±10% fab tolerance work, Hammerstad-Jensen is fully adequate.
Yes, but the via is a discontinuity. A through-hole via has a capacitive stub (the unused lower barrel) and an inductive section that shift the impedance locally. For frequencies below ~1 GHz this is usually acceptable with standard vias. Above 1 GHz, use via-in-pad, back-drilled (controlled depth) vias, or micro-vias on HDI boards to minimize the stub. Also ensure that the reference plane follows the signal trace on the destination layer — if L1 uses L2 as its ground, after transitioning to L3 the reference should be L2 or L4, with via stitching nearby to provide a low-impedance return path.
Conductor loss (skin effect) and dielectric loss together set the total attenuation. For a 50 Ω 1 oz copper microstrip on standard FR4 at common frequencies: at 1 GHz ≈ 0.10–0.15 dB/cm; at 2.4 GHz ≈ 0.20–0.30 dB/cm; at 5 GHz ≈ 0.40–0.60 dB/cm. A 10 cm WiFi trace at 5 GHz can lose 4–6 dB — meaningful before your LNA. Enter a frequency in the 'Frequency (GHz)' field in this tool to compute conductor and dielectric attenuation separately for your specific geometry and material.