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RFrftools.io

PCB Stack-Up Builder

Build your board layer by layer, then compute controlled impedance for any trace — microstrip, stripline, differential pairs, or coplanar waveguide.

⠇⠇SMSoldermask (top)
mm
⠇⠇CuL1 — Signal
⠇⠇PPPrepreg
mm
⠇⠇CuL2 — Ground
⠇⠇CoreCore — FR4
mm
⠇⠇CuL3 — Power
⠇⠇PPPrepreg
mm
⠇⠇CuL4 — Signal
⠇⠇SMSoldermask (bottom)
mm
1.555 mm0.0250Soldermask (top)1 ozL1 — Signal0.100Prepreg0.5 ozL2 — Ground1.200Core — FR40.5 ozL3 — Power0.100Prepreg1 ozL4 — Signal0.0250Soldermask (bottom)

Trace Specification

Results

Configure trace parameters and run the calculation to see results.

How Controlled Impedance Works

The PCB Stack-Up Tool designs layer configurations with impedance calculation for controlled-impedance boards — essential for RF designs (50-ohm matching), high-speed digital (DDR4/5, PCIe Gen4/5, USB4), and EMC compliance. Signal integrity engineers use this to achieve +/-10% impedance tolerance (standard fab) or +/-5% (advanced RF fab) while maintaining layer-to-layer isolation. Per IPC-2141A and Hammerstad-Jensen equations (validated to +/-1% by IEEE MTT-S), characteristic impedance Z0 depends on four parameters: trace width W, dielectric height H above reference plane, copper thickness T, and effective dielectric constant Er_eff. For microstrip (outer layer), Er_eff ranges from 0.6xEr to 0.85xEr because field exists partly in air; for stripline (inner layer), Er_eff = Er because field is fully contained in dielectric. FR4 dielectric constant varies from 4.6 at 1 MHz to 4.2 at 5 GHz (9% shift) per the Djordjevic-Sarkar dispersion model, changing calculated impedance by 4-5%. Rogers RO4350B maintains Er = 3.48 +/-0.05 from 1-10 GHz, which is why RF designs above 2 GHz specify controlled-Er laminates per IPC-4101. Standard FR4 loss tangent (tan_delta = 0.02) causes 0.5-1 dB/cm attenuation at 5 GHz; low-loss materials achieve 0.1-0.15 dB/cm. Propagation delay t_pd = sqrt(Er_eff)/c0 differs 14% between microstrip (~6.1 ps/mm on FR4) and stripline (~7.1 ps/mm). For DDR4 at 3200 MT/s (312 ps unit interval), length matching between layers must account for this velocity difference — a 10mm trace mismatch causes 61 ps skew on microstrip versus 71 ps on stripline.

Worked Example

Problem
You are designing a 2.4 GHz WiFi front-end on a JLC standard 4-layer board (1.6 mm total, FR4, 1 oz outer copper). The RF trace on L1 must be 50 Ω. What trace width do you need?
Solution
The JLC standard 4-layer uses a 0.1 mm prepreg between L1 and L2. L2 is the ground reference. Copper weight is 1 oz (34.8 µm).

For microstrip on FR4 with H = 0.100 mm, T = 0.035 mm, εᵣ = 4.5, the Hammerstad-Jensen formula gives Z₀ ≈ 44 Ω at W = 0.200 mm. Using the Solve function with Target Z₀ = 50 Ω → solved width ≈ 0.158 mm (εᵣ_eff ≈ 3.39).

Propagation delay: t_pd = √3.39 / 299.8 ≈ 6.13 ps/mm. A 25 mm antenna feed trace adds ~153 ps — negligible for most 2.4 GHz matching network tolerances.

Fab note: “L1/L4 microstrip: W = 0.16 mm, Z₀ = 50 Ω ±10%, per IPC-2141A. Route over solid L2/L3 reference planes.”

Practical Tips

  • ✓Verify fab's actual stackup before finalizing design — JLC, PCBWay, OSHPark publish exact layer thicknesses and Er values. Generic FR4 assumptions cause 5-10% impedance error that may exceed +/-10% spec.
  • ✓Use 1oz copper on signal layers for tighter impedance control — 2oz copper increases effective trace width, shifting Z0 by 3-5 ohm and requiring width adjustment per IPC-2141A Table 4-1.
  • ✓Route impedance-controlled traces over continuous reference planes only — slots, cutouts, or via antipads in the ground plane below disturb return current, degrading impedance by 10-30% and increasing EMI by 6-10 dB per Henry Ott.
  • ✓Add impedance test coupons to Gerber package — without TDR-measurable coupons, fab cannot verify compliance and failures are untraceable per IPC-TM-650 2.5.5.7. Most fabs charge extra for controlled impedance without coupons.
  • ✓For differential pairs (USB, PCIe, HDMI): maintain trace spacing constant through entire route including vias and connectors — even 2mm of wider spacing increases Zdiff by 5-8% and degrades return loss per IEEE 802.3.
  • ✓At GHz frequencies (>2 GHz RF, >5 Gbps digital): specify low-loss laminate (Rogers, Isola I-Speed, FR4-HF) — standard FR4 tan_delta = 0.020 causes 0.5-1 dB/cm attenuation that accumulates over longer traces.
  • ✓Check soldermask effect — 25um soldermask over microstrip lowers Z0 by 1-2 ohm. Use embedded microstrip model in calculations or request unmasked impedance areas for RF traces.
  • ✓For asymmetric stripline (typical inner layers): use correct formula. A trace on L2 of 4-layer board has 0.1mm prepreg above and 1.2mm core below — symmetric formula overestimates Z0 by 10-25%.

Common Mistakes

  • ✗Using 1 MHz Er value (4.6) at GHz frequencies — Er drops to 4.2 at 5 GHz per Djordjevic-Sarkar, shifting impedance by 5%. Always use frequency-corrected Er or specify controlled-Er laminate for RF.
  • ✗Placing controlled impedance trace on inner layer without checking asymmetry — JLC 4-layer has 0.1mm prepreg and 1.2mm core creating 12:1 height ratio. Use asymmetric stripline formula, not symmetric.
  • ✗Forgetting that copper thickness affects impedance — 0.5oz to 2oz copper shift changes effective width and Z0 by 3-8 ohm. Recalculate when changing copper weight.
  • ✗Running impedance-controlled traces through via fields without ground stitching — each un-stitched ground gap creates impedance discontinuity reflecting 3-5% of signal energy per Johnson/Graham.
  • ✗Assuming same propagation delay on all layers — microstrip (Er_eff=3.4) propagates at 6.1 ps/mm; stripline (Er_eff=4.5) at 7.1 ps/mm. Length matching between layers requires 14% length adjustment.
  • ✗Specifying controlled impedance without test coupon — fab cannot TDR-verify impedance without coupon. Any impedance failure in production is undiagnosable. Always request coupon and TDR report.
  • ✗Changing stackup mid-design without recalculating — adding a layer or changing core thickness invalidates all previously calculated trace widths. Re-run impedance calculations after any stackup change.

Frequently Asked Questions

Controlled impedance means manufacturing PCB traces to specific characteristic impedance (50 ohm for RF, 100 ohm differential for USB/PCIe). Per transmission line theory, when trace length exceeds lambda/10 (approximately 15mm at 1 GHz on FR4), impedance mismatch causes reflections. A 50-ohm trace driving 75-ohm load reflects 20% of signal energy (VSWR 1.5:1), degrading eye diagrams by 15-40% in high-speed interfaces.
Standard PCB fabs (JLC, PCBWay, OSHPark) achieve +/-10% controlled impedance per IPC-6012D Class 2. Advanced RF fabs offer +/-5% for premium pricing. A 50-ohm trace at +/-10% gives 45-55 ohm range, resulting in worst-case VSWR of 1.22:1 (return loss 20 dB) — acceptable for most RF below 6 GHz and digital below 10 Gbps.
Microstrip: outer layer trace with dielectric below and air/soldermask above. Effective Er is lower (field partly in air), giving higher impedance for same width and faster propagation (6.1 ps/mm). Stripline: inner layer trace buried between two ground planes. Full Er applies, giving lower impedance for same width and slower propagation (7.1 ps/mm). Stripline provides 6-10 dB better isolation and EMC shielding per Johnson/Graham.
CPWG places coplanar ground copper adjacent to trace plus ground plane below. Use for: (1) thick substrates where H > 0.3mm makes microstrip trace too wide; (2) RF transitions at connectors/chip pads needing well-defined ground; (3) designs requiring lateral shielding. The coplanar gap provides additional impedance tuning parameter. CPWG achieves +/-3% tighter tolerance than microstrip per Rogers design guides.
FR4 Er drops from 4.5-4.7 at 1 MHz to 4.2-4.4 at 1 GHz to 4.0-4.2 at 5 GHz per Djordjevic-Sarkar dispersion model. This 9% variation shifts calculated impedance by 4-5%. The tool applies frequency correction when you enter operating frequency. For designs above 2 GHz, use measured datasheet values or specify Rogers/Isola materials with tightly controlled Er (+/-1.5%).
Symmetric stripline has trace centered between two reference planes with equal dielectric height above and below. Asymmetric stripline (common on inner layers) has unequal heights — L2 on 4-layer board typically has 0.1mm prepreg above and 1.2mm core below (12:1 ratio). Symmetric formula overestimates Z0 by 10-25% for asymmetric geometries. Always select correct model for accurate calculations.
t_pd = sqrt(Er_eff)/c0, where c0 = 299.8 mm/ns. For 50-ohm FR4 microstrip (Er_eff approximately 3.4), t_pd = 6.1 ps/mm. For stripline (Er_eff = 4.5), t_pd = 7.1 ps/mm. DDR4 at 3200 MT/s requires <10 ps skew within byte lanes — allowing only 1.6mm length mismatch on microstrip. The tool displays propagation delay for current geometry to compare against interface specifications.
Hammerstad-Jensen microstrip formula is accurate to +/-1-2% for typical geometries (0.1 < W/H < 10, T/H < 0.2) per IEEE MTT-S validation. Stripline formulas achieve +/-1.5%. Accuracy degrades at extreme W/H ratios, via transitions, and near copper pours. For +/-3% or tighter tolerance requirements, complement calculations with 2.5D (Polar SI9000, HyperLynx) or 3D EM simulation (CST, HFSS).
Yes, but via is a discontinuity. Through-hole via has capacitive stub (unused barrel below signal layer) and 1-2 nH inductance that locally shift impedance. Below 1 GHz this is usually acceptable. Above 1 GHz: use via-in-pad, back-drill stubs per IPC-6012E, or HDI micro-vias. Ensure reference plane continuity on destination layer and add via stitching within 2mm for low-inductance return path per Johnson/Graham.
Conductor loss (skin effect) plus dielectric loss: for 50-ohm 1oz microstrip on FR4 — at 1 GHz: 0.10-0.15 dB/cm; at 2.4 GHz: 0.20-0.30 dB/cm; at 5 GHz: 0.40-0.60 dB/cm. A 10cm WiFi trace at 5 GHz loses 4-6 dB — significant before LNA. Rogers RO4350B reduces this to 0.08-0.12 dB/cm at 5 GHz. Enter frequency in the tool to compute attenuation for your specific geometry.