Power ElectronicsFebruary 8, 20267 min read

Buck Converter Design Guide: Inductor, Capacitor, and Efficiency

How to design a synchronous buck converter from scratch. Calculates duty cycle, inductor value, output capacitor, and estimates efficiency with worked examples.

When to Use a Buck Converter vs. LDO

A linear regulator (LDO) is simple and quiet but dissipates all excess voltage as heat: P = (V_in − V_out) × I_out. At 12V→3.3V at 1A, that's 8.7W lost — requiring a heatsink and wasting 73% of input power.

A buck converter achieves 85–95% efficiency but requires an inductor, output capacitor, and either a dedicated controller or integrated power IC. The crossover point where a buck becomes worth the complexity:

V_{in} - V_{out} > \frac{P_{thermal\_budget}}{I_{out}}

For typical PCB designs: if (V_in − V_out) × I_out > 0.5W, consider a buck.

Fundamental Equations

Duty cycle (continuous conduction mode):

D = \frac{V_{out}}{V_{in} \cdot \eta}

For first-pass calculations, assume η = 0.88 (88% efficiency).

Inductor value for a given ripple current (typically 20–40% of I_out):

L = \frac{V_{out} \cdot (1 - D)}{\Delta I_L \cdot f_{sw}}

Output capacitor for a given output ripple voltage:

C_{out} = \frac{\Delta I_L}{8 \cdot f_{sw} \cdot \Delta V_{out}}

This is the ideal minimum. In practice, add ESR of the capacitor: ΔV_ESR = ΔI_L × ESR.

Worked Example: 12V → 5V at 2A

Given: V_in = 12V, V_out = 5V, I_out = 2A, f_sw = 400 kHz

1. Duty cycle: D = 5 / (12 × 0.88) = 0.473 (47.3%)

2. Ripple current (30% of I_out): ΔI_L = 0.6A

3. Inductor: L = 5 × (1 − 0.473) / (0.6 × 400,000) = 11 µH → use 10 µH standard

4. Output capacitor (ΔV = 50 mV): C = 0.6 / (8 × 400,000 × 0.05) = 3.75 µF → use 10 µF for margin

5. Inductor peak current: I_peak = 2 + 0.3 = 2.3A — select inductor rated ≥2.5A

Inductor Selection

Key specs:

Inductance value ±20% is fine; ferrite cores drift with DC bias
Saturation current > I_peak (never saturate the core — efficiency collapses)
DCR (DC resistance) — lower is better; P = I²×DCR
SRF (self-resonant frequency) > 2× f_sw

For 10 µH at 2A, a Würth 74437324100 or TDK SLF12555T-100M4R3 are common choices.

Capacitor Selection

For output capacitors, ceramic X5R or X7R is preferred. Avoid Y5V (high capacitance loss vs. DC bias). Electrolytic can be used in parallel for bulk capacitance.

For input capacitors, place a 10–100 µF bulk cap near the converter plus 1 µF ceramic at the IC pins. The switching current drawn from the input is pulsed — poor input decoupling causes noise across the board.

Efficiency Losses

Main loss mechanisms: 1. Conduction loss: I²×R in the FETs and inductor DCR 2. Switching loss: P_sw = 0.5 × V_in × I_out × t_sw × f_sw (proportional to f_sw) 3. Gate charge loss: P_g = Q_g × V_gs × f_sw per FET 4. Inductor core loss: frequency and flux-dependent, from the core datasheet

At 400 kHz with typical components, expect 88–92% efficiency. At 1 MHz, switching losses increase — efficiency may drop to 83–87% unless you use advanced FETs.

Model your design with the Buck Converter Calculator to compute duty cycle, inductor size, and capacitor requirements before placing a component order.

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