How to Pick the Right Decoupling Capacitor: SRF, ESL, and the Math Behind Bypass Networks

Why Decoupling Isn't as Simple as "Slap a 100 nF on It"

Every engineer has heard the rule of thumb: put a 100 nF capacitor next to every IC power pin. It works — until it doesn't. When your FPGA draws 20 A transient currents at 500 MHz, or your ADC has a spurious tone that traces back to supply noise at 800 MHz, that lonely 100 nF cap is no longer enough. Understanding *why* requires looking at three parasitic parameters that most datasheets bury in fine print: ESR, ESL, and the self-resonant frequency they create.

The Real Model of a Capacitor

A physical capacitor isn't a pure capacitance. It's a series RLC circuit:

where $C$ is the nominal capacitance, $L$ is the equivalent series inductance (ESL), and $R$ is the equivalent series resistance (ESR). At low frequencies the capacitive reactance $X_C = 1/(2\pi f C)$ dominates. At high frequencies the inductive reactance $X_L = 2\pi f L$ takes over. Right in the middle, the two cancel and you're left with the ESR — the lowest impedance the capacitor will ever present. That crossover point is the self-resonant frequency (SRF):

Below the SRF the part behaves like a capacitor. Above it, it behaves like an inductor. This is the single most important concept in decoupling design: a capacitor only decouples effectively in a band around its SRF.

Key Parameters and What They Mean for Your PDN

Your power distribution network (PDN) has a target impedance, often derived from:

For a 1.0 V rail supplying an FPGA with 5 A transients and a 3% ripple budget, that's $Z_{\text{target}} = 1.0 \times 0.03 / 5 = 6\,\text{m}\Omega$. That's a tough number to hit, and it has to be maintained across the entire bandwidth of interest.

Here's where ESR and ESL matter:

• ESR sets the impedance floor at SRF. A typical 100 nF 0402 MLCC might have an ESR of 10–50 mΩ. If your target impedance is 6 mΩ, a single cap can't do the job.
• ESL determines how quickly impedance rises above SRF. A 0402 package might have 0.5 nH of ESL; a 0201 might be 0.3 nH. Lower ESL pushes the effective bypass range higher in frequency.

Worked Example: Bypassing a 1.0 V FPGA Rail

Let's walk through a real scenario. We need to keep $Z_{\text{PDN}} < 6\,\text{m}\Omega$ up to 500 MHz.

Step 1: Choose a capacitor. We select a 100 nF 0402 X7R MLCC with ESR = 20 mΩ and ESL = 0.5 nH. Step 2: Find the SRF.

Plugging through: $f_{\text{SRF}} \approx 22.5\,\text{MHz}$. At this frequency the impedance equals the ESR: 20 mΩ.

Step 3: Check impedance at 500 MHz. Well above SRF, the impedance is dominated by the ESL:

That's 260× our target. The 100 nF cap is essentially invisible at 500 MHz.

Step 4: Add a higher-frequency cap. A 1 nF 0201 cap with ESR = 50 mΩ and ESL = 0.3 nH gives:

At 500 MHz its impedance is roughly $2\pi \times 500 \times 10^6 \times 0.3 \times 10^{-9} \approx 0.94\,\Omega$ — still too high for a single cap, but now we're in the right frequency neighborhood.

Step 5: Parallel capacitors. Placing $N$ identical capacitors in parallel divides the impedance by $N$. To hit 6 mΩ at the SRF of the 100 nF cap (where $Z = 20\,\text{m}\Omega$), we need:

For the 500 MHz range we need a separate bank of 1 nF caps (or even smaller values) targeting that band. This is why real PDN designs use multiple capacitor values — each covering a different frequency decade.

The Effective Bypass Range

A useful concept is the frequency range over which a capacitor keeps impedance below your target. The upper bound of this range can be estimated by finding the frequency where $X_L = Z_{\text{target}}$:

For our 100 nF cap with 0.5 nH ESL and a 20 mΩ target (single cap): $f_{\text{upper}} = 0.02 / (2\pi \times 5 \times 10^{-10}) \approx 6.4\,\text{MHz}$. That's the frequency above SRF where the cap stops being useful on its own. Below SRF there's a symmetric lower bound. The calculator computes both for you.

Common Pitfalls

• Ignoring ESL from PCB vias and traces. The 0.5 nH ESL in a datasheet is the package alone. A via to an internal power plane can add another 0.5–1.0 nH, cutting SRF significantly. Keep decoupling caps on the same layer as the IC or use very short, wide via connections.
• Anti-resonance between parallel caps. Two different-value caps in parallel can create a high-impedance peak between their SRFs. Simulation or careful value spacing is essential.
• Assuming ceramic caps hold their value. A 100 nF X7R cap under 1.0 V DC bias in an 0402 package might actually be 60–70 nF. Check the manufacturer's DC bias curves.

Try It

Plug your capacitor values, ESR, ESL, and target impedance into the calculator and instantly see the SRF, impedance at your frequency of interest, effective bypass range, and how many caps you actually need. Open the Decoupling Capacitor Selection Calculator and take the guesswork out of your next PDN design.