FDTD Via Simulation: Why Your 10 Gbps Signal Hates Via Stubs

The Via Is Not Just a Hole

At 100 MHz, a 0.3 mm drill via on a 1.5 mm FR-4 board is electrically invisible — it measures a fraction of an ohm of resistance and maybe 0.5 nH of inductance. Plug that into your SPICE model and move on. But route a 10 Gbps SerDes lane through the same via on a 12-layer backplane and the story is completely different. The unused lower portion of the via barrel — the stub — behaves as a shorted transmission line stub, and its quarter-wave resonance can create a deep notch directly in your signal band.

An FDTD (Finite-Difference Time-Domain) simulation solves Maxwell's equations on a 3D grid, so it captures the full electromagnetic behavior of the via transition: the impedance discontinuity at the pad, the barrel inductance, the stub resonance, and the capacitive loading of the anti-pad. The FDTD S-Parameter Simulator tool lets you run this in the browser in seconds, without a full 3D EM solver license.

Setting Up the Simulation

Here are the exact parameters for modeling a through-via on a standard 1.5 mm FR-4 PCB carrying a 10 Gbps signal:

A few notes on these choices. The 3.0 mm trace width is correct for 50 Ω on 1.5 mm FR-4 with 1oz copper (confirmed by a microstrip impedance calculator). The via aspect ratio of 5:1 (1.5 mm depth, 0.3 mm drill) is at the moderate end — most PCB manufacturers are comfortable to 8:1 with standard drill bits and to 12:1 with laser-assist. The center frequency of 2.4 GHz with a 4 GHz span covers DC to 4.4 GHz, which captures both the Nyquist frequency of a 10 Gbps NRZ signal (5 GHz) and the first stub resonance, which for this geometry lands around 3.8 GHz.

What the FDTD Engine Is Doing

When you click Run, the simulator discretizes the via geometry onto a Yee grid — a staggered 3D mesh where electric and magnetic field components are offset by half a cell in space and time. A Gaussian pulse is injected at Port 1 (the microstrip feed end), and the time-domain fields are recorded at Port 1 (reflected) and Port 2 (transmitted) until the energy decays. The S-parameters come from the ratio of the Fourier transforms:

The Normal mesh density uses roughly 10 cells per wavelength at the center frequency, which is adequate for a first-pass assessment. Fine mesh will increase cell count by 8× and take proportionally longer, but is needed when the via barrel diameter is less than 3× the mesh cell size.

Interpreting the S11 and S21 Results

For a through-via with no back-drilling on 1.5 mm FR-4, you will see something like this in the output plots:

S21 (insertion loss): Flat and near 0 dB from DC up to roughly 2 GHz, then a progressive rolloff, with a sharp notch at approximately 3.8 GHz dropping to −15 to −20 dB. This is the stub resonance. S11 (return loss): Below −20 dB at low frequency, rising to −10 to −15 dB near the stub resonance frequency, then improving again at higher frequencies as the via impedance coincidentally re-matches.

The stub resonance frequency is the critical number. For a through-via where the signal enters at the top layer and exits at layer 3 (of a 10-layer board), the stub is the portion of the barrel below layer 3. Its resonant frequency is:

where $v_p = c / \sqrt{\varepsilon_r}$ is the propagation velocity in the dielectric and $L_{stub}$ is the physical stub length. For FR-4 (εr = 4.4): $v_p = 3 \times 10^8 / \sqrt{4.4} \approx 1.43 \times 10^8$ m/s. A 1.0 mm stub resonates at 35.7 GHz — harmless for 10 Gbps. A full 1.5 mm stub (signal exits at layer 1, nothing back-drilled) resonates at 23.8 GHz — still above the Nyquist, but only by a factor of 4.7. Run the simulation at a 10 GHz span and you will see the notch creep in by 8 GHz.

Effect of Via Drill Diameter

Now change the Via Diameter parameter from 0.3 mm to 0.5 mm and re-run. You should observe:

• The stub resonance frequency shifts slightly lower (larger barrel has more capacitance, pulling frequency down)
• S21 insertion loss at low frequency worsens slightly due to increased pad capacitance
• S11 at DC-to-1 GHz degrades by 2–4 dB as the larger anti-pad capacitance mismatches the trace impedance

This confirms the SI rule of thumb: minimize via drill diameter for high-speed signals, not just to hit aspect ratio targets, but to reduce the via capacitance that lowers local impedance. For a 0.3 mm drill on 1.5 mm FR-4, via impedance is roughly 35–40 Ω — already 10–15 Ω below the 50 Ω system impedance. Some designs compensate by reducing the anti-pad diameter to shrink the capacitance.

When to Back-Drill

Back-drilling removes the stub by counter-boring from the opposite side of the board, leaving only a short stub remnant (typically 0.1–0.2 mm drill-to-layer clearance). It adds cost — expect $150–300 per panel — but the improvement is dramatic: the notch disappears from the signal band entirely.

The rule of thumb is simple: if the stub resonance from the Via Stub Resonance calculator lands within 2× the signal Nyquist frequency, back-drill. For 10 Gbps NRZ (5 GHz Nyquist), back-drill any stub that resonates below 10 GHz. For 25 Gbps PAM4, that threshold is 25 GHz — which means back-drilling is nearly always required on backplane designs.

What to Do with the Results

Once the simulation confirms a stub resonance problem, your options in order of increasing cost are:

1. Re-route to a shallower layer transition. If the signal can exit at layer 2 instead of layer 6, the stub is much shorter.
2. Reduce drill diameter. Smaller via, lower capacitance, slightly higher resonance frequency.
3. Add a via-in-pad with back-drill. Best SI result, highest cost.
4. Use blind or buried vias. Eliminates the stub entirely; significantly increases fabrication complexity.

Run the FDTD simulation at each stage to confirm the resonance has moved out of band before sending the design to fab. An hour of simulation time is far cheaper than a PCB respin.

Use the FDTD S-Parameter Simulator to model your via geometry directly in the browser.