Predicting Radiated Emissions Before FCC Testing: A PCB Engineer's Walkthrough

Pre-Compliance Scanning Is Not Enough on Its Own

Your Raspberry Pi-sized SBC has a 100 MHz processor clock, a 2 cm² power loop between the switching regulator and its bulk capacitor, and a 0.5 m USB cable for the host interface. Your PCB reviewer flagged both during design review. The pre-compliance scan confirmed the concern: harmonics at 300 MHz, 500 MHz, and 700 MHz are within 6 dB of the FCC Part 15 Class B limit at 3 meters.

You have four weeks before the scheduled FCC test. Spinning a new board takes three. You need to know exactly which changes will fix the problem — and which are wasted effort.

The EMI Radiated Emissions Estimator models both differential-mode (DM) loop radiation and common-mode (CM) cable radiation, applies the spectral envelope of a trapezoidal clock, and runs Monte Carlo over measurement uncertainty to give you a yield figure against the FCC limit. That's the analysis you need.

Understanding the Two Radiation Mechanisms

Radiated emissions from digital PCBs come from two physically distinct mechanisms, and fixing one does nothing for the other.

Differential-mode radiation comes from currents circulating in closed loops on the PCB — typically the switching regulator power loop, the decoupling capacitor return path, or a high-speed signal trace paired with its return. The field from a small loop falls off as $1/r^2$ in the near field but transitions to $1/r$ in the far field. The FCC measures at 3 m, firmly in the far field for frequencies above about 16 MHz.

The electric field from a small DM loop at distance $r$ is approximately:

where $f$ is in Hz, $I$ is the loop current in amps, and $A$ is the loop area in m².

Common-mode radiation comes from currents flowing in the same direction on a cable (no differential return). Even microamp CM currents on a half-meter cable create efficient antennas at frequencies where the cable length approaches λ/4. A 0.5 m cable resonates near 150 MHz — squarely in the range of the 100 MHz clock harmonics.

Baseline Analysis: The Problem Design

Enter the following into the EMI Radiated Emissions Estimator:

The tool generates the spectral envelope of the 100 MHz clock with a 1 ns rise time. A trapezoidal waveform has a spectral envelope that rolls off at 20 dB/decade above $1/\pi t_r$, which for a 1 ns rise time is about 318 MHz. Below that corner frequency, odd harmonics (100, 300, 500, 700 MHz…) fall on a relatively flat envelope. Above it, harmonics fall rapidly.

With the baseline inputs, the tool reports:

• 300 MHz (3rd harmonic): DM estimate 42 dBµV/m, CM estimate 48 dBµV/m, FCC Class B limit 40 dBµV/m. CM exceeds limit by 8 dB.
• 500 MHz (5th harmonic): DM estimate 35 dBµV/m, CM estimate 44 dBµV/m, FCC limit 47 dBµV/m. CM is 3 dB under — but the 95th percentile Monte Carlo result pushes above the limit.
• 700 MHz (7th harmonic): Both sources fall below the limit at 47 dBµV/m.

The CM cable current is the dominant problem at 300 MHz and above. This matches the pre-compliance scan pattern perfectly.

Why the USB Cable Dominates at High Frequencies

At 100 MHz, a 0.5 m cable is λ/6. Not efficient. At 300 MHz, it's λ/2 — a half-wave dipole. Radiation efficiency peaks. At 500 MHz the cable is a full wave, efficiency dips slightly, but 5 µA CM current is still enough to approach the limit.

The DM loop at 2 cm² is not negligible, but the $f^2$ dependence in the field equation works against it: even though it contributes strongly at low harmonics, the small area limits it. The cable, acting as a CM antenna, does not have the same area limitation — it radiates as a dipole, which scales much more favorably.

This is why adding decoupling capacitors alone will not solve this problem. Decoupling reduces DM loop currents. The CM current on the USB cable comes from parasitic coupling between the board's common-mode noise voltage and the cable shield or ground reference. You need a CM choke on the USB lines.

The Fix: Three Targeted Changes

Update the tool inputs to reflect the proposed design changes:

Re-run with 100,000 Monte Carlo trials. Results:

• 300 MHz: DM 33 dBµV/m, CM 28 dBµV/m, 95th percentile 36 dBµV/m vs. 40 dBµV/m limit. 4 dB margin.
• 500 MHz: DM 22 dBµV/m, CM 24 dBµV/m, 95th percentile 30 dBµV/m vs. 47 dBµV/m limit. 17 dB margin.
• 700 MHz: Both sources well below limit.

Yield (fraction of MC trials below the FCC limit across all harmonics) goes from 34% to 98%.

Implementation Notes

Tightening the power loop from 2 cm² to 0.5 cm² means moving the switching regulator's bulk input capacitor as close as possible to the V_in and GND pins, with a short, wide return path. Reducing loop area by 4× reduces DM field strength by 4× (linear, 12 dB), not 16× — area appears linearly in the field equation, not squared. The CM choke needs to be placed on the USB lines close to the connector, on the PCB side, not the cable side. A 90Ω CM impedance at 100 MHz is sufficient — parts like the TDK ACM2012 or Wurth 742792090 are common choices. One component, inserted in series, reduces CM current by 14 dB in this scenario. Slowing the rise time from 1 ns to 5 ns shifts the spectral rolloff corner from 318 MHz down to 64 MHz. The 300 MHz harmonic, previously on the flat part of the spectrum, now sits on the −20 dB/decade slope and is attenuated by roughly 14 dB. A 22Ω series resistor in the clock net costs nothing in BOM or board area.

All three changes can be implemented with a PCB re-layout and one added component. No hardware re-spin of the processor section is needed.

EMI Radiated Emissions Estimator