Calculating MOSFET Losses in H-Bridge Motor Drivers

Why Motor Driver Losses Matter

You've picked your MOSFETs, drawn up the H-bridge, and now the motor spins. Looks good, right? Not so fast. The difference between a motor driver that works on your bench and one that survives in real-world conditions often comes down to thermal design — and that starts with knowing exactly how much power each FET is burning.

Motor driver losses break down into two key categories: conduction losses (resistive heating when the FET is on) and switching losses (energy wasted during each on/off transition). Get these numbers wrong, and you'll either over-engineer your heatsink and waste precious board space, or under-spec it and watch your FETs thermal-throttle at the worst possible moment. Most engineers skip the detailed loss calculations early on and regret it later when they're debugging thermal runaway issues at 3 AM before a demo.

We'll break down the math, walk through a real example with actual numbers you might see in a brushed DC motor application, and show you how to get answers fast with our Motor Driver Power Dissipation calculator.

Conduction Loss: The Steady-State Tax

When a MOSFET is fully on, it acts like a tiny resistor — characterized by its $R_{DS(on)}$. This is the on-resistance, and while it's small (often just a few milliohms in modern power FETs), it's never zero. In a PWM-driven H-bridge with synchronous recirculation, the motor current always flows through two FETs: a high-side and a low-side FET during the on-time, and two FETs again while the current recirculates during the off-time (TI SLVA504A). So the bridge's conduction loss does not depend on the duty cycle $D$:

Here's something that trips people up constantly: $R_{DS(on)}$ gets worse with temperature. That nice low value in the datasheet? That's at 25°C. At 100°C, expect it to be 1.5× to 2× higher depending on the FET technology. Always design with the "hot" resistance, not the room-temperature spec. I've seen too many designs that looked great on paper at 25°C but turned into space heaters once they hit operating temperature.

The duty cycle decides which FETs share that loss, not how big it is. With high-side recirculation, one high-side FET conducts for the whole period and dissipates $I^2 R_{DS(on)}$; the low-side FET conducts only during the on-time, $I^2 R_{DS(on)} D$, but it is also the FET that is hard-switched, so at high duty it is the hottest one in the bridge.

Switching Loss: The Speed Tax

Every MOSFET transition from off to on (or back) involves a brief moment where both voltage and current are high. During this transition, the FET is in its linear region — neither fully on nor fully off. The energy lost per transition approximates to:

The problem is that rise and fall times depend on your gate drive circuit, PCB layout, and a bunch of other variables that are hard to nail down precisely. Our calculator takes a single transition time $t_{sw}$ (50 ns unless you enter another), with rise and fall taken equal, and with sign-magnitude PWM only one FET is hard-switched each period (TI SLVA504A):

This formula captures the key insight: switching loss scales linearly with switching frequency. Cranking up switching frequency to kill audible noise or reduce output ripple? Just remember that comes with a real thermal penalty. Double the frequency, double the switching losses. There's no free lunch.

Gate charge $Q_g$ is essentially a measure of how much charge you need to pump into the gate capacitance to switch the FET. Lower gate charge means faster switching with the same gate driver, and so shorter transitions. The charge also costs power of its own: the two complementary FETs that switch each period draw $P_{gate} = 2 \times Q_g \times V \times f_{sw}$ (IR AN-1070), which heats the gate driver, not the FETs. The calculator reports it separately and counts it in the driver's efficiency.

Worked Example: 24V, 10A Brushed DC Motor Driver

Let's break down losses for a typical scenario — something you might encounter driving a medium-power brushed DC motor in a robotics or industrial application:

Note that we're using the hot $R_{DS(on)}$ value here — 8 milliohms at 100°C. The datasheet probably shows something like 5 mΩ at 25°C, but we're being realistic about operating conditions.

Conduction loss per conducting FET:

That's 10 amps squared times 8 milliohms. Two FETs carry the motor current at any instant, so the bridge conducts 1.6 W — at 75% duty cycle or any other.

Switching loss (one hard-switched FET, 50 ns transition):

At 20 kHz switching frequency, the switching losses are relatively modest compared to conduction losses. But watch what happens when we change that frequency later.

Hottest FET (the low side: on-time conduction plus switching): Total bridge loss (two conducting FETs, one hard-switched):

So we're dissipating just under 2 watts across the bridge. In a typical H-bridge, you've got two high-side FETs and two low-side FETs, and at any given moment one high-side and one low-side FET are conducting — never all four, which is why adding up four FETs at 0.72 W each would overstate the loss at 2.88 W. The gate driver adds $2 \times 50 \times 10^{-9} \times 24 \times 20000 = 0.048$ W for the two FETs that switch each period.

Estimated driver efficiency:

The supply delivers $24 \times 10 \times 0.75 = 180$ W at 75% duty cycle. Counting the bridge and the gate drive against it:

Not bad. But notice what happens if you quadruple switching frequency to 80 kHz to push PWM noise out of the audible range: switching loss jumps to 0.96 W and the hottest FET from 0.84 W to 1.56 W, the gate drive to 0.19 W, total bridge loss climbs to 2.56 W, and you've added heat with zero motor performance benefit. Efficiency drops to around 98.5%. That extra 0.9 W might not sound like much, but in a thermally constrained enclosure, it's the difference between reliable operation and thermal shutdown.

Design Implications

Quick practical takeaways that actually matter in real designs:

Conduction loss dominates at low switching frequencies. Running 10–20 kHz? Focus on low $R_{DS(on)}$ FETs. Spending an extra dollar on a FET with half the on-resistance will save you way more in thermal management costs. In our example, conduction losses were nearly 7× higher than switching losses. Switching loss takes over at high frequencies. Above 50 kHz, gate charge $Q_g$ becomes the critical parameter. You can have the lowest $R_{DS(on)}$ in the world, but if your gate charge is high, you'll burn watts every time you switch. This is where those fancy GaN FETs start to shine — their low gate charge makes high-frequency operation practical. Duty cycle moves conduction between FETs, not the total. Switching losses depend on frequency and load current, period. Whether you're running 25% or 75% duty cycle, you're still switching at the same rate, so switching losses stay constant. The bridge's conduction loss stays constant too, because two FETs carry the current at every instant; what the duty cycle changes is which FET runs hottest — the low side, which also switches, at high duty. Thermal derating is mandatory. Our example shows 0.84 W in the hottest FET — manageable in theory, but tight in constrained spaces. If you're using an SOT-23 package with minimal copper, you're going to have problems. An SO-8 with exposed pad and decent copper pour? Much more reasonable. Always check the thermal resistance from junction to ambient for your specific package and PCB layout.

When the Numbers Get Uncomfortable

If bridge losses push junction temperature past safe limits (and most MOSFETs start getting unhappy above 125°C junction temperature), you've got four moves:

Lower $R_{DS(on)}$ — Pick a bigger FET with more silicon area, or parallel multiple FETs. Two FETs in parallel cut conduction losses in half, though you've doubled your switching losses and board area. Sometimes that trade makes sense. Lower $Q_g$ — Switch to a faster-switching FET with lower gate charge. Modern superjunction MOSFETs and GaN devices excel here. The downside is they're often more expensive and can be touchier about gate drive design. Lower $f_{sw}$ — Drop your switching frequency. You'll accept more ripple current in the motor or more audible noise, but thermal problems often disappear. Going from 40 kHz to 20 kHz cuts switching losses in half. Better thermal path — Use an exposed pad package, route to thicker copper planes, add a heatsink, or improve airflow. Sometimes the answer isn't a different FET, it's better mechanical design. A few square inches of 2oz copper can work wonders.

Try It Yourself

Plug your actual parameters into the Motor Driver Power Dissipation calculator. It's the fastest way to sanity-check your FET selection before committing to a layout. Iterate on switching frequency, FET selection, and duty cycle until your thermal budget makes sense. The calculator will show you exactly where your losses are coming from and help you make informed trade-offs. Way better than discovering you need a redesign after the first prototype run.