PDN Impedance: Cavity Resonance & Decoupling Tips

The Invisible Problem on Every High-Speed PCB

Your 1.0V core rail looks clean on the scope. The LDO regulation spec says 50mV ripple, you measure 30mV. Everything looks fine — until the FPGA fails to configure, the DDR controller throws occasional ECC errors, or the RF front-end spurs appear at unexpected offsets.

Power delivery network impedance is the culprit in more board failures than most engineers realize. The voltage rail isn't just ripple at the switching frequency — it's a transmission medium with frequency-dependent impedance, resonances, and anti-resonances that the processor's current demand excites across a bandwidth from DC to several hundred megahertz. Getting a flat, low PDN impedance profile across that entire bandwidth is the engineering goal, and it requires modeling cavity resonances, not just scattering bulk capacitors around the board and hoping for the best.

This walkthrough uses the PDN Impedance Analyzer to design the power delivery network for a mid-range FPGA core rail. We'll see exactly why a seemingly clean rail can still cause intermittent failures and how to fix it systematically.

Target Impedance: Working Backwards from dV Budget

Start with the target impedance calculation:

For a 1.0V core rail with ±5% ripple budget and a worst-case transient of 2A (LUT switching), the target is:

This 25 mΩ target must be met from DC to the highest frequency at which significant current transients occur — for this FPGA, approximately 300 MHz. Most engineers stop here and throw capacitors at the problem. That's a mistake.

Enter the VRM parameters: 5 mΩ DCR and 10 MHz bandwidth (the closed-loop bandwidth of the POL regulator, and the highest the tool accepts). There is no VRM inductance field: the tool derives the VRM's output inductance from those two, $L_{VRM} = R_{DC} / (2\pi f_{BW})$, which is 80 pH here. In series with it sits the board inductance, the path from the regulator to the planes through vias, traces and connector: an input of its own, 1 nH by default, which this walkthrough keeps. These parameters determine where the VRM stops providing effective regulation and where the capacitors must take over. The regulator corrects voltage droop up to its 10 MHz bandwidth, but the feed path already reaches 25 mΩ at about 3.6 MHz, so above a few megahertz you're on your own — the capacitors have to hold the rail stable.

Plane-Pair Cavity Resonances

Here's where it gets interesting. A 100mm × 80mm four-layer board with 4 mil FR-4 between power and ground planes isn't just a passive conductor — it's a resonant cavity. The parallel planes form a dielectric-loaded waveguide that supports standing wave modes, and those modes appear like LC circuits in the PDN impedance profile.

The lowest cavity resonance frequency is:

For the (m=1, n=0) mode on a 100mm board with FR-4 (ε_r = 4.3):

Enter the board into the tool: width 100 mm, length 80 mm, dielectric constant 4.3, plane-pair separation 0.1016 mm (4 mil), and the default loss tangent of 0.02. Set the port where the FPGA's power pins are, x = 25 mm, y = 20 mm, leave the port size at its default, a 1 mm square, and sweep from 1 kHz to 2 GHz. The port needs a size because the cavity's modal sum never converges at a single point. The cavity-alone trace on the impedance plot immediately shows the anti-resonance peaks: sharp spikes at 723 MHz (TM10), 904 MHz (TM01), and 1.16 GHz (TM11), where the cavity looks like a high-impedance LC resonator. The resonance table lists four more modes below 2 GHz, but this port sits on a null of every one of them, so they don't show as spikes, and the table marks them not seen at this port. Leave the port blank and the tool puts it at the board's one-third point, (33.3 mm, 26.7 mm) here, where all seven show: $\cos(m\pi/3)$ is never zero, so no mode has a null there. At the board center the first three would disappear too, since the center is a null of every mode with an odd index. Between these peaks, the cavity impedance actually drops — the planes are helping you. But without decoupling capacitors, the impedance exceeds the 25 mΩ target from 3.6 MHz to 266 MHz, most of the band where your FPGA is pulling current transients, and near 84 MHz it reaches tens of ohms, where the feed inductance resonates with the planes' 3.0 nF. Its one dip below the target in that range, from 266 to 299 MHz, is the planes' own series resonance: their 3.0 nF against the spreading inductance between the port and the rest of the plane.

These cavity modes are why you can't just rely on "the planes are a big capacitor" — they are, but only at specific frequencies. At the anti-resonance peaks, they're worse than useless.

Capacitor Selection: Why the Database Matters

The tool's optimizer draws on a built-in database of seven MLCCs: 1 nF, 10 nF, 100 nF and 1 μF in 0402, 10 μF in 0603, 47 μF in 0805, and 100 μF in 1206, each with a typical ESR and ESL. This isn't just convenience — it's critical because a capacitor's self-resonant frequency (SRF) determines where it provides its minimum impedance:

A 100 nF 0402 capacitor with 400 pH ESL resonates at 25 MHz. Below that frequency it behaves as a capacitor; above it, as an inductor. A 1 nF 0402 with 300 pH ESL resonates at 291 MHz. Effective PDN design staggers multiple capacitor values to maintain a cascade of resonances below the target impedance — a technique called capacitor value interleaving.

You can't just pick arbitrary values and hope they work. The ESL matters more than most engineers think. I've seen boards with twenty 100 nF capacitors that still fail because they're all the same package size, all resonating at the same frequency, leaving gaps in the impedance profile where transients cause voltage droop.

Running the Genetic Algorithm Optimizer

Set the optimization target: 25 mΩ target impedance, with a maximum of 20 capacitors total. The tool sets the band it designs for and judges: from the bottom of the sweep to 80% of the board's first cavity mode (or to the top of the sweep, if that comes first), here 1 kHz to 578 MHz, below TM10 at 723 MHz, which covers the 300 MHz this FPGA needs. Above that edge the plane-pair cavity, not the capacitors, sets the impedance. The size of the genetic algorithm is set by the lane: 150 generations of 200 candidate designs on the free lane, 400 of 400 on the paid lane.

The GA ranks designs in two stages. The first is one number: the worst ratio of impedance to target anywhere in that band, since with a flat target the worst point sets the droop. Below 1, the target is met. Designs within 0.1 dB of the lowest worst case count as tied, and among them the tool takes the one that keeps the rest of the band lowest, judged against the target where the budget can reach it and against the floor, the lowest impedance any design within the budget achieves, where it cannot. The result lists those frequencies as unreachable, each range with its floor, and the verdict counts them. After the last generation, the best designs found are refined one move at a time — add, remove or swap one capacitor — judged on the same two stages with the true worst case between grid points, until no single move improves the ranking; a rerun with another random seed returns the same design. It does not penalize capacitor count, so it usually spends the whole budget. Finding the smallest count that still meets the impedance spec is your job, and it matters, because every capacitor costs money, board area, and assembly time.

On the free lane the best design stops improving by the third generation, and the optimizer selects:

• 1× 1 μF 0402 (SRF 7 MHz)
• 1× 100 nF 0402 (SRF 25 MHz)
• 14× 10 nF 0402 (SRF 85 MHz)
• 4× 1 nF 0402 (SRF 291 MHz)

That design fails. The profile starts at the regulator's 5 mΩ and crosses the target at about 2.7 MHz; it stays above it up to 45 MHz, peaking at 46 mΩ near 16 MHz, and rises above it again from 175 to 262 MHz, where it peaks at 78 mΩ at 238 MHz. That is the worst case the tool reports, +9.9 dB over the target. From 381 MHz the profile climbs toward the first cavity mode, and the tool marks 473–578 MHz as unreachable: no 20 parts from its library get below 25.11 mΩ there. The verdict covers the whole band, but this FPGA draws no significant current transients above 300 MHz, so the violations that matter here are the ones below it. If you were driving a faster device, you'd need to extend the low-impedance region higher in frequency.

What's remarkable is that the GA discovers the same capacitor staging strategy that experienced power integrity engineers use intuitively. It's not magic — it's just systematically exploring the design space faster than you could by hand.

The Convergence History Tells You If You Need More Capacitors

Check the convergence history chart in the results. A plateau with the fitness still above 1 means the algorithm can't find a solution with the capacitors it is allowed. The library is fixed, so the lever is the budget: increase the maximum capacitor count.

A curve that falls below 1 means the target is met, and how far below tells you how much margin the budget buys. This is useful information for cost optimization. The curve is the worst ratio on the frequency grid, though, while the verdict judges the refined worst case, which the tool finds between grid points, so the verdict can read a little higher than the curve's last value.

For the 20-capacitor budget in this example, the curve flattens at 3.12 by the third generation and never moves again: the GA can't find a mix of 20 parts from the library that holds this board to 25 mΩ. Raise the budget and run it again. At 40 capacitors the best design still misses, by 1.9 dB; at 50 it passes, at 23.6 mΩ; at 80 the worst case falls to 14.0 mΩ, 5.0 dB under the target, with 72 of the 80 parts in 1 nF and 10 nF. Stepping the budget down until a run fails is how you find the smallest BOM that works.

The Anti-Resonance Problem

One result the tool highlights immediately: the anti-resonance between the 10 nF and 1 nF capacitors at about 238 MHz. This is a classic trap. Above their 85 MHz SRF the 10 nF caps are inductive, while the 1 nF caps stay capacitive up to 291 MHz, and so do the planes up to their series resonance near 280 MHz; in between, the inductive 10 nF bank and the capacitive 1 nF bank and planes form a parallel LC circuit with a high impedance peak. The tool shows this as the 78 mΩ spike at 238 MHz, and if your processor happens to pull a current transient with significant energy at that frequency, you'll see voltage droop even though you have plenty of capacitance on the board.

The fix is to add a damping resistor in series with one of the capacitor values (typically 0.1–1 Ω, which kills the Q of the resonance without significantly increasing the impedance elsewhere), or to add an intermediate value to bridge the gap. The tool's library has no value between 1 nF and 10 nF, so when you raise the budget the GA takes the brute-force route instead: more of both. At 80 capacitors the anti-resonance is still there, near 250 MHz, but down to 14.0 mΩ.

This is the central insight of PDN design: you're not just bypassing noise, you're designing an impedance spectrum. The capacitors, the VRM output impedance, the plane cavity modes, and the via inductances all interact to create a complex frequency-dependent impedance profile. The GA discovers what decades of experience-driven heuristics have codified — and it does it in under 30 seconds, without requiring you to manually calculate every resonance and anti-resonance.

You can iterate on the design, adjust the target impedance, change board dimensions, or swap VRM topologies and immediately see the impact on the impedance profile. That feedback loop is what turns PDN design from black art into engineering.