PCB Stack-Up Design & Controlled Impedance: A Practical Guide

Why Stack-Up Design Matters

Every high-speed or RF PCB starts with the same question: *what layer stack do I need to hit my target impedance?* Get it wrong and you'll fight signal integrity problems all the way through layout, fab, and bring-up. Get it right and controlled impedance falls out naturally from your geometry.

This guide covers the physics behind PCB impedance, how to choose materials and layer counts, and how to use our PCB Stack-Up Builder to design your stack interactively.

The Physics: How Trace Geometry Sets Impedance

A PCB trace is a transmission line. Its characteristic impedance $Z_0$ depends on four things:

1. Trace width ($w$) — wider traces have lower impedance
2. Dielectric height ($h$) — the distance from trace to the nearest reference (ground) plane
3. Dielectric constant ($\varepsilon_r$) — higher $\varepsilon_r$ means lower impedance
4. Copper thickness ($t$) — minor effect, but included in accurate models

The relationship is not linear. The Hammerstad-Jensen (1980) model gives the most widely-used closed-form approximation for microstrip:

where $u = w_{\text{eff}} / h$ is the normalized width and $\varepsilon_{\text{eff}}$ is the effective dielectric constant (a weighted average of the substrate and air above the trace). This formula is accurate to better than 1% for $0.1 \leq w/h \leq 10$.

Trace Modes: Microstrip vs. Stripline vs. CPWG

Microstrip

The most common geometry: a trace on an outer layer with a ground plane below. The electromagnetic field is partially in the dielectric, partially in air, so $\varepsilon_{\text{eff}} < \varepsilon_r$.

When to use: Single-ended signals on outer layers — most digital I/O, moderate-speed clocks, RF traces where you need easy access for probing.

Embedded Microstrip

Same as microstrip but with a soldermask overlay. The cover increases $\varepsilon_{\text{eff}}$ and *lowers* $Z_0$ by a few ohms. Always account for this in production — bare-board impedance measurements won't match the final assembly.

Stripline

A trace buried between two ground planes. The field is entirely contained in the dielectric, so $\varepsilon_{\text{eff}} = \varepsilon_r$ exactly. Stripline has better shielding and lower radiation than microstrip, but narrower traces for the same impedance.

When to use: Inner-layer routing for sensitive high-speed signals (DDR4/5 data, PCIe, USB 3.x), any trace that needs good isolation from adjacent signals.

Asymmetric Stripline

When the trace isn't centred between the two reference planes (common in real stack-ups), the impedance shifts. The IPC-2141A correction factor handles this:

where $h_1$ is the distance to the nearer plane and $b = h_1 + h_2 + t$.

Differential Pairs

Two coupled traces carrying complementary signals. The differential impedance $Z_{\text{diff}}$ depends on both the single-ended $Z_0$ and the coupling between traces (set by edge-to-edge spacing $s$):

Tight coupling (small $s$) reduces $Z_{\text{diff}}$ below $2 Z_0$. For 100 $\Omega$ differential, target roughly 50–55 $\Omega$ single-ended with spacing equal to the trace width.

CPWG (Coplanar Waveguide with Ground)

A trace flanked by coplanar ground pours on the same layer, plus a ground plane below. CPWG uses elliptic integrals for the impedance calculation and offers excellent high-frequency performance because the return current stays close to the signal.

When to use: mmWave designs, RF connectors (SMA launch pads), any trace where you need tight impedance control with minimal via transitions.

Material Selection

For mixed RF + digital boards, consider a hybrid stack: Rogers on the outer layers for RF, FR4 core for digital routing and cost control.

Choosing Your Layer Count

• 2-layer: Hobby boards, simple circuits. Limited impedance control.
• 4-layer: The sweet spot for most designs. Signal–Ground–Power–Signal gives two controlled-impedance surfaces.
• 6-layer: Adds inner signal layers for dense routing. Common for DDR4 memory interfaces.
• 8-layer: Server, networking, and complex RF. Allows dedicated RF layers with Rogers material.

DFM Tips

1. Keep copper layers symmetric — odd layer counts cause warping during lamination
2. Minimum prepreg thickness: 75 $\mu$m — thinner prepreg is unreliable in standard fab processes
3. Specify impedance on your fab drawing — most fabs will adjust trace width ±10% to hit your target
4. Account for etch factor — outer layers etch more than inner layers; your fab house knows their process
5. Use the same dielectric material for all layers when possible — mixed-material stacks add cost and lead time

Try It: Interactive Stack-Up Builder

Our PCB Stack-Up Builder lets you:

• Drag-and-drop layers to build any stack configuration
• Choose from 8 preset stacks (2L hobby through 8L hybrid Rogers)
• Pick real materials — FR4, Rogers RO4003C/RO4350B/RO3003, Megtron 6, PTFE
• Compute impedance for all 8 trace modes (microstrip, stripline, differential, CPWG)
• Solve for trace width given a target impedance
• Export CSV for your fab drawing
• See a live cross-section with proportional layer thicknesses and trace overlay

All calculations run in your browser using Hammerstad-Jensen (1980), Cohn (1954), and IPC-2141A formulas — no server round-trip, instant results.

References

• Hammerstad, E. & Jensen, O. "Accurate Models for Microstrip Computer-Aided Design." IEEE MTT-S Digest, 1980.
• Cohn, S.B. "Characteristic Impedance of the Shielded-Strip Transmission Line." Proc. IRE, 1954.
• IPC-2141A. "Design Guide for High-Speed Controlled Impedance Circuit Boards."
• Wadell, B.C. *Transmission Line Design Handbook.* Artech House, 1991.
• Bogatin, E. *Signal and Power Integrity — Simplified.* 3rd ed., Pearson, 2018.