PDN Impedance Analyzer: Taming Plane-Pair Resonances With Genetic-Algorithm Decoupling

The Problem: A 1.0 V FPGA Rail That Won't Stay Quiet

Modern FPGAs draw 30 A or more from a 1.0 V core rail. The target impedance is simple to calculate:

That target must be met from below 100 kHz (where the VRM regulates) up to 1 GHz (where the package decoupling takes over). In between, the PCB's power distribution network (PDN) is on its own — and that's where resonances hide.

The board is 100 mm x 120 mm, FR-4 with $\varepsilon_r = 4.3$ and $\tan\delta = 0.02$. The power–ground plane pair is spaced 0.1 mm apart (4-mil dielectric). Let's see what happens when we throw this into the PDN Impedance Analyzer at rftools.io/tools/pdn-impedance.

Plane-Pair Cavity Resonances

Two parallel copper planes separated by a thin dielectric form a resonant cavity — exactly like a rectangular microwave resonator, just very thin. The resonant frequencies are:

where $a$ and $b$ are the board dimensions, $m$ and $n$ are mode indices, and $c$ is the speed of light.

For our 100 mm x 120 mm board with $\varepsilon_r = 4.3$:

• TM₁₀ at 722 MHz
• TM₀₁ at 602 MHz
• TM₁₁ at 940 MHz

At each resonance, the impedance between the planes spikes. If one of these spikes pokes above the target impedance, the FPGA sees a voltage droop at that frequency — and high-speed I/O starts generating spurious EMI.

The Cavity Model: Novak's Green's Function

The analyzer uses the Green's function approach from Istvan Novak's formulation. The impedance between two points on the plane pair is:

where $d$ is the dielectric thickness, $k_x = m\pi/a$, $k_y = n\pi/b$, $k = \omega\sqrt{\mu_0 \varepsilon_0 \varepsilon_r}$, and $\delta_m$ is the Neumann factor (1 for $m=0$, 2 otherwise).

The probe point is placed at the center of the board — worst case for odd-odd modes, and representative of a typical BGA location.

Why One Capacitor Value Isn't Enough

A single MLCC has a series resonance (SRF) where its impedance drops to just its ESR:

A 100 nF / 0402 cap with 400 pH ESL resonates around 25 MHz. Below that, it looks capacitive and reduces low-frequency impedance. Above that, it looks inductive — and *adds* to the problem.

To cover the full 100 kHz to 1 GHz band, you need a mix of capacitor values:

But how many of each? That's a combinatorial optimization problem.

The Genetic Algorithm Approach

The analyzer uses a genetic algorithm (GA) to find the optimal capacitor mix. Each individual in the population is a vector of 7 integers — the count of each capacitor type — constrained to a maximum total of 30 caps (our board has limited real estate near the BGA).

Fitness function: For each candidate solution, the tool computes the combined impedance of the cavity (parallel combination of plane-pair impedance with all the capacitors in parallel), then finds the worst-case ratio of $|Z_{PDN}|$ to $Z_{target}$. The GA minimizes this ratio. Selection: Tournament selection with $k=4$. Four random individuals are drawn; the one with the lowest fitness (least violation) wins. Crossover: Two-point crossover on the gene vector, with constraint repair — if the child exceeds the max cap count, the algorithm randomly trims capacitor counts until the constraint is satisfied. Mutation: Each gene has a probability of $\pm 1$ adjustment, again followed by constraint clamping.

Running the Optimizer

We set up the following parameters in the tool:

• Board: 100 mm x 120 mm, $\varepsilon_r = 4.3$, $\tan\delta = 0.02$
• Plane spacing: 0.1 mm
• Supply: 1.0 V, 30 A, 5% ripple budget
• VRM: 0.5 mΩ output resistance, 100 nH loop inductance
• Frequency range: 100 kHz to 1 GHz
• Max decoupling capacitors: 30

The GA ran with 400 individuals over 400 generations. Here's what the optimizer found.

Impedance Profile

The red curve shows the bare plane-pair impedance with no decoupling — massive spikes at each cavity resonance. The green curve shows the optimized PDN with all 30 capacitors placed. The blue horizontal line is our 1.67 mΩ target.

The optimizer met the target across the full band. The worst violation was −0.5 dB *below* target — meaning we have margin.

Optimized Capacitor Mix

The GA converged on this solution:

Notice the distribution: the heaviest allocation (8 caps) goes to 100 nF — the workhorse of mid-band decoupling. The 10 nF and 1 µF values get 5-6 each to cover the transition zones. The extreme values (100 µF and 100 pF) get just 2 each — enough to anchor the ends of the band without wasting board space.

GA Convergence

The fitness (worst-case $|Z_{PDN}|/Z_{target}$ ratio) dropped from ~2.5 in generation 1 to ~0.85 by generation 150, and plateaued there. This tells us the GA found a near-optimal solution well before the 400-generation limit. Running 200 generations would have been sufficient for this board size.

Design Insights

1. Plane Spacing Matters More Than You Think

Reducing the plane-pair spacing from 0.2 mm to 0.1 mm roughly doubles the interplane capacitance ($C = \varepsilon_0 \varepsilon_r A / d$). This shifts the cavity resonances and can eliminate the need for 2-3 decoupling caps. If your stackup allows it, tight plane spacing is the cheapest PDN improvement.

2. ESL Dominates Above 100 MHz

Above the SRF, a capacitor looks inductive. The ESL — not the capacitance — determines high-frequency performance. The optimizer's preference for 0201 packages at high frequencies reflects their lower ESL (200-300 pH vs 400-800 pH for 0402/0603).

3. Don't Ignore the VRM Loop Inductance

The VRM's output inductance ($L_{VRM}$) creates an impedance rise at low frequencies. If $L_{VRM}$ is too high, even large bulk caps can't bridge the gap between the VRM's bandwidth and the decoupling network. The tool models this as a series RL from the VRM.

4. The 30-Cap Constraint Is Realistic

With a 15 mm x 15 mm BGA footprint, you can fit roughly 30-40 decoupling caps within a 5 mm halo around the package. The constraint forces the optimizer to make smart tradeoffs rather than brute-forcing with hundreds of caps.

Comparing With a Hand-Picked Solution

A common rule of thumb is to place 10x 100 nF, 5x 10 µF, and 5x 1 µF — a 20-cap solution. Running this through the analyzer shows it fails above 200 MHz because there's no high-frequency coverage. Adding even 5x 10 nF caps fixes the 200-500 MHz range, but the 500 MHz-1 GHz region still has resonance spikes.

The GA's solution uses all 7 cap values and allocates counts based on where the impedance needs the most help. No rule of thumb can match this level of frequency-domain awareness.

Practical Notes

Board size sensitivity: Larger boards have lower-frequency cavity resonances. A 200 mm x 250 mm server board might see TM₁₀ at 290 MHz — well within the decoupling band. Smaller boards (50 mm x 50 mm) push resonances above 1 GHz where they're less problematic. Dielectric constant: High-$\varepsilon_r$ laminates (like Rogers or Megtron) lower resonant frequencies. This is usually beneficial for decoupling (more interplane capacitance), but can surprise you if resonances shift into your signal bandwidth. Loss tangent: Higher $\tan\delta$ damps resonance peaks. FR-4's $\tan\delta \approx 0.02$ provides modest damping. Low-loss laminates ($\tan\delta \approx 0.002$) have sharper resonance spikes that are harder to suppress.

Conclusion

PDN design is a frequency-domain problem that spans four decades. Plane-pair cavity resonances create impedance spikes that hand-placed decoupling can miss entirely. The genetic algorithm approach finds a capacitor mix that covers the full band while respecting a realistic cap count budget.

Try the tool at rftools.io/tools/pdn-impedance — input your board dimensions, stackup, and power requirements, and let the optimizer find the decoupling solution.

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*Related tools: PCB Trace Impedance, Via Impedance, Decoupling Capacitor, Bypass Cap Resonance*