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Decoupling Capacitor Selection Calculator

Calculate decoupling capacitor SRF, impedance at target frequency, and number of caps needed for power integrity. Includes ESR/ESL modeling. Free, instant results.

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Formula

fSRF=1/(2π√(ESL⋅C)),Z=√(ESR2+(XC−XL)2)f_SRF = 1 / (2π√(ESL·C)), Z = √(ESR² + (X_C − X_L)²)
C— Capacitance (F)
ESR— Equivalent series resistance (Ω)
ESL— Equivalent series inductance (H)
f_SRF— Self-resonant frequency (Hz)
Z— Impedance (Ω)

How It Works

The Decoupling Capacitor Calculator determines optimal capacitor values and placement for power supply noise suppression — essential for digital IC power integrity, FPGA PDN design, and EMC compliance. PDN engineers use this to achieve target impedance below 100 mohm across DC to 500 MHz, preventing supply noise from corrupting signal integrity.

Per Smith's 'High-Speed Digital System Design,' capacitive reactance Xc = 1/(2 x pi x f x C) sets the low-frequency impedance, but ESL (equivalent series inductance, typically 0.5-2 nH) and ESR create a resonant peak at f_SRF = 1/(2 x pi x sqrt(ESL x C)). A 100 nF 0402 capacitor with 0.7 nH ESL resonates at 19 MHz; above this, it becomes inductive and loses decoupling effectiveness.

Per IPC-2152 PDN guidelines, achieving flat impedance requires multiple capacitor values in parallel: 10 uF (resonates at 500 kHz) covers low frequencies; 100 nF (resonates at 19 MHz) covers mid-band; 10 nF (resonates at 60 MHz) and 1 nF (resonates at 200 MHz) extend coverage to hundreds of MHz. Each value overlaps the next's inductive region.

Placement is critical — per Johnson/Graham, every mm of trace adds approximately 1 nH inductance to the capacitor's effective ESL. A 100 nF capacitor placed 10mm from an IC power pin has 10 nH added inductance, shifting SRF from 19 MHz down to 5 MHz and degrading high-frequency decoupling by 12 dB. Place decoupling capacitors within 3mm of power pins.

Worked Example

Problem: Design decoupling for a 1.8V FPGA with 200mA transient current in 2ns (di/dt = 100 MA/s), target PDN impedance < 50 mohm at 100 MHz.

Solution per Smith:

  1. Target impedance: Z_target = deltaV_max / deltaI = 0.09V (5% of 1.8V) / 0.2A = 450 mohm... too high. Use 90mV / 2A transient = 45 mohm target.
  2. At 100 MHz, need total capacitance to provide Xc < 45 mohm: C > 1/(2 x pi x 100e6 x 0.045) = 35 nF
  3. But ESL limits performance: need multiple capacitors with overlapping SRF bands.
  4. Design: 2x 10 uF (bulk, SRF ~500 kHz), 4x 100 nF (SRF ~19 MHz), 4x 10 nF (SRF ~60 MHz), 2x 1 nF (SRF ~200 MHz)
  5. Parallel impedance at 100 MHz: 4x 10 nF capacitors in parallel = 4/(2 x pi x 100e6 x 10e-9) = 15 mohm from capacitance; ESR and ESL add ~10 mohm.
  6. Total: ~25 mohm at 100 MHz — meets 45 mohm target with margin.
Placement: All capacitors within 3mm of FPGA power pins on same layer (no vias in path).

Practical Tips

  • ✓Use 0402 or 0201 packages for best high-frequency performance — 0402 has 0.7 nH ESL versus 1.2 nH for 0805, extending usable bandwidth by 30% per TDK application notes.
  • ✓Follow the '1-2-4 rule': 1x 10 uF bulk, 2x 100 nF per power pin, 4x 10 nF distributed across die area — provides flat impedance from 100 kHz to 200 MHz per Intel FPGA design guides.
  • ✓Measure PDN impedance with VNA — simulation accuracy is +/-30%; actual measurement reveals resonances from PCB planes and via fields that dominate above 100 MHz.

Common Mistakes

  • ✗Using single large capacitor value — a 10 uF capacitor provides <1 mohm at 10 kHz but >100 ohm at 100 MHz due to ESL. Must use multiple values for broadband coverage per IPC-2152.
  • ✗Ignoring via inductance in decoupling path — a single 0.3mm via adds 1.5 nH, comparable to capacitor's ESL. Use multiple vias or place capacitor on same layer as power pin per Johnson/Graham.
  • ✗Placing capacitors far from IC — every 5mm of trace adds 5 nH inductance, shifting SRF lower by sqrt(5/0.7) = 2.7x and reducing high-frequency effectiveness by 8 dB.

Frequently Asked Questions

Provide local charge storage to supply transient current demands without voltage droop. Per Smith, an IC switching 1A in 1ns needs 1nC of charge; if PDN inductance is 10 nH, supply voltage would droop 10V without local capacitors. Decoupling capacitors provide this charge within the IC's timing requirements.
Match SRF to noise frequency. Per IPC-2152: 10-100 uF for <1 MHz (bulk); 100 nF for 1-30 MHz (primary decoupling); 10 nF for 30-100 MHz; 1-10 nF for >100 MHz. Use multiple values — no single capacitor covers more than 1 decade effectively. IC manufacturers' datasheets often specify required values.
Only for bulk/low-frequency decoupling below 1 MHz. Electrolytics have high ESR (0.1-1 ohm) and ESL (5-20 nH) compared to MLCC ceramics (ESR < 10 mohm, ESL < 1 nH). Per Murata guidelines, use electrolytics for >10 uF bulk storage, MLCC for all high-frequency decoupling.
All real capacitors have parasitic inductance (ESL) from leads and internal electrodes. At f_SRF = 1/(2 x pi x sqrt(ESL x C)), capacitive and inductive reactances cancel, leaving only ESR. Above SRF, the capacitor is inductive. For 100 nF MLCC: SRF typically 15-25 MHz; for 10 nF: 50-80 MHz; for 1 nF: 150-300 MHz.
Rule of thumb per Intel/Xilinx design guides: minimum 1 capacitor per power pin, plus 1 bulk capacitor per power rail. For FPGAs: 0.5-1 capacitor per power pin for low-speed; 2-3 per pin for high-speed (>500 MHz) designs. Total count often 50-200 capacitors for large FPGAs, consuming 10-20% of board area.

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