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ESD Clamp Diode Selection

Calculate ESD clamp diode peak current, power dissipation, and clamping ratio. Verify TVS protection for IEC 61000-4-2 compliance.

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Formula

Ipk=(VESDVcl)/Z,Ppk=Vcl×IpkI_pk = (V_ESD − V_cl) / Z, P_pk = V_cl × I_pk
V_clClamp voltage (V)
ZDischarge path impedance (Ω)

How It Works

The ESD Clamp Selection Calculator determines TVS diode parameters for IEC 61000-4-2 protection — essential for USB, HDMI, Ethernet, and any externally-accessible interface. Hardware engineers use this to select protection devices that clamp 8 kV ESD events to safe voltages (<5.5V for 3.3V ICs) within the <1 ns rise time of contact discharge.

Per IEC 61000-4-2 and JEDEC JESD22-A114, ESD protection requires clamping voltage V_cl below the IC's absolute maximum rating while handling peak currents of 15-30 A. For Level 4 contact discharge (8 kV), peak current I_pk = (V_ESD - V_cl) / 330 ohm (human body model impedance). With V_cl = 15V: I_pk = (8000-15)/330 = 24.2 A. Peak power P_pk = V_cl x I_pk = 363 W, but only for approximately 1 ns.

The clamping ratio V_cl/V_ESD indicates protection efficiency. Per ON Semiconductor application notes, good TVS diodes achieve V_cl/V_ESD < 0.005 (15V clamp for 8 kV event). The voltage overshoot during the first nanosecond depends on TVS junction capacitance — lower capacitance (<0.5 pF) is critical for high-speed interfaces (USB 3.0, HDMI 2.1) where capacitance causes impedance mismatch and eye degradation.

Per JEDEC and USB-IF specifications, ESD protection must not degrade signal integrity. For USB 3.0 (5 Gbps), TVS capacitance must be <0.5 pF; for USB 3.2 Gen 2 (10 Gbps), <0.25 pF. Higher capacitance TVS devices are acceptable for lower-speed interfaces (USB 2.0: <5 pF; GPIO: <15 pF).

Worked Example

Problem: Select ESD protection for USB Type-C port (3.3V logic, IEC 61000-4-2 Level 4 contact, USB 3.2 Gen 2 at 10 Gbps).

Solution per IEC 61000-4-2:

  1. IC maximum rating: 3.3V logic with 5.5V absolute max (typical for 3.3V CMOS)
  2. Required V_cl: < 5.5V at peak ESD current
  3. Level 4 contact: V_ESD = 8 kV; I_pk = (8000-5.5)/330 = 24.2 A
  4. Search for TVS: V_cl < 5.5V at 24 A, capacitance < 0.25 pF for 10 Gbps
  5. Select: Nexperia PESD5V0C1BSF (V_cl = 8V at 16A, 0.15 pF, SOD-923 package)
  6. Verify at 24 A: V_cl approximately 12V (extrapolate from datasheet curve) — too high!
  7. Alternative: TI TPD1E10B06 (V_cl = 4.5V at 30A, 0.18 pF) — meets requirements
  8. Clamping ratio: 4.5/8000 = 0.00056 — excellent
Placement: Within 2mm of USB connector pins, ground via directly under TVS pad for minimum inductance. Series resistor (10-33 ohm) between connector and TVS helps limit dV/dt.

Practical Tips

  • Use multi-channel TVS arrays for connectors with multiple pins — per Nexperia, TVS arrays (4-8 channels) save board space and provide matched capacitance for differential pairs. Cost approximately $0.10-0.30 per channel in volume.
  • Add small series resistor (10-47 ohm) between connector and TVS — per TI application notes, this limits dV/dt during ESD event and helps TVS turn on faster, reducing peak overshoot by 20-30%.
  • Verify ESD performance with actual IEC 61000-4-2 testing — per ON Semi, PCB layout affects clamping voltage by 10-30%. Ground inductance, trace length, and via placement all impact real-world performance.

Common Mistakes

  • Selecting TVS by standoff voltage alone — per ON Semi, standoff voltage is DC operating voltage, not clamping voltage. A 5V standoff TVS may have 9V clamping voltage at 8 kV ESD, damaging 3.3V ICs. Always check V_cl at rated ESD current.
  • Ignoring capacitance for high-speed interfaces — per USB-IF, >1 pF TVS causes 5-10% eye closure at 5 Gbps. For 10+ Gbps interfaces, use TVS arrays with <0.25 pF per line. Standard TVS (5-15 pF) are only suitable for low-speed signals.
  • Placing ESD protection far from connector — per JEDEC guidelines, every mm of trace between connector and TVS allows ESD spike to propagate before clamping. Place TVS within 2mm of connector pin with direct ground via under the device.

Frequently Asked Questions

Per Littelfuse: ESD TVS is optimized for fast transients (<1 ns rise time) with peak currents of 15-30 A for <100 ns duration. Surge TVS handles slower transients (8/20 us waveform per IEC 61000-4-5) with currents of 100-1000 A for milliseconds. ESD TVS has lower capacitance (0.1-5 pF) and faster response; surge TVS has higher energy handling. Different threat profiles require different devices.
Per JEDEC: IEC 61000-4-2 contact discharge uses 150 pF / 330 ohm with <1 ns rise time and 24 A peak at 8 kV — system-level testing. HBM (Human Body Model) uses 100 pF / 1500 ohm with approximately 10 ns rise time and 5.3 A peak at 8 kV — component-level testing. IEC 61000-4-2 is 4x harsher in peak current. Products must pass both when applicable.
Not recommended per ON Semi: zener diodes have approximately 10 ns response time versus <1 ns for TVS. During the first 10 ns of an ESD event, zener provides no clamping — the full ESD spike reaches the IC. TVS diodes are specifically designed for sub-nanosecond response. Use zeners only for slow transients (surge protection, not ESD).
Per JEDEC: V_cl must be below the protected IC's absolute maximum rating, typically 0.3V above Vcc for CMOS inputs. For 3.3V logic: V_max typically 3.6V to 5.5V depending on process. For 1.8V logic: V_max typically 2.0V to 3.0V. Check IC datasheet for exact value. Add margin: select TVS with V_cl at least 10% below V_max.
Per IEC 61000-4-2: (1) Perform ESD testing per the standard using calibrated ESD simulator; (2) Apply discharges to all accessible ports at required levels (typically Level 4 = 8 kV contact, 15 kV air); (3) Monitor for functional upset (soft errors) and damage (hard failures); (4) Measure actual clamping voltage with oscilloscope and current probe if failures occur. Pre-compliance testing available from ESD generator vendors.

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