Skip to content
RFrftools.io
PCB

PCB Stackup Impedance Calculator

Calculate trace width for target impedance across PCB stackup configurations. Select layer count, dielectric, and copper weight for 50 ohm or custom Z0. Free, instant results.

Loading calculator...

Formula

A=Z060εr+12+εr−1εr+1(0.23+0.11εr),WH=8eAe2A−2A = \frac{Z_0}{60}\sqrt{\frac{\varepsilon_r+1}{2}} + \frac{\varepsilon_r-1}{\varepsilon_r+1}\left(0.23+\frac{0.11}{\varepsilon_r}\right),\quad \frac{W}{H} = \frac{8e^A}{e^{2A}-2}

Reference: Wheeler (1977); Pozar "Microwave Engineering" 4th ed.

Z₀— Target characteristic impedance (Ω)
εᵣ— Dielectric constant
A— Wheeler intermediate parameter
W/H— Trace width to height ratio
H— Dielectric layer thickness (mm)

How It Works

The PCB Stackup Builder designs layer configurations for controlled impedance and signal integrity — essential for RF front-ends, high-speed digital interfaces (DDR4/5, PCIe Gen4/5), and EMC compliance. Hardware engineers use this to achieve 50-ohm (+/-10%) impedance while maintaining 6-10 dB crosstalk isolation between signal layers.

Per IPC-2141A and Johnson/Graham's 'High-Speed Digital Design,' stackup determines three critical parameters: (1) characteristic impedance via dielectric height H and trace width W; (2) crosstalk via signal-to-signal layer spacing; (3) EMC performance via ground/power plane placement. The Hammerstad-Jensen equations achieve +/-1% impedance accuracy for W/H ratios between 0.1 and 10.

FR4's dielectric constant varies 4.6 (1 MHz) to 4.2 (5 GHz) per Djordjevic-Sarkar model — a 9% shift that changes calculated impedance by 4-5%. Rogers RO4350B maintains Er = 3.48 +/-1.5% to 10 GHz, which is why RF designs above 2 GHz specify controlled-Er materials per IPC-4101. Standard fab tolerance is +/-10% impedance; advanced RF fabs achieve +/-5%.

Propagation delay differs between microstrip (6.1 ps/mm on FR4) and stripline (7.1 ps/mm) due to different effective Er. For DDR4 at 3200 MT/s (312 ps UI), a 10mm length mismatch between outer and inner layer traces causes 10 ps skew — 3% of the timing budget. Length matching must account for layer-specific propagation velocity.

Worked Example

Problem: Design 4-layer stackup for USB 3.0 (90-ohm differential) and WiFi 2.4 GHz (50-ohm single-ended) on same board using JLC standard process.

Solution per IPC-2141A:

  1. JLC 4-layer standard: 1.6mm total, L1-L2 prepreg 0.1mm, L2-L3 core 1.2mm, L3-L4 prepreg 0.1mm
  2. Layer assignment: L1 = signal (USB TX, WiFi RF), L2 = GND, L3 = VCC, L4 = signal (USB RX)
  3. For 50-ohm microstrip on L1 (H=0.1mm, Er=4.3): W = 0.19mm (7.5 mils) per Hammerstad-Jensen
  4. For 90-ohm differential on L1 (Zdiff = 2 x Zodd): S = 0.16mm spacing at W = 0.12mm
  5. Verify via TDR simulation or fab capability table
  6. Propagation delay L1: 6.14 ps/mm; length match USB pair within 0.82mm for <5ps skew
Fab notes: 'L1/L4 microstrip Z0=50 ohm +/-10%, Zdiff=90 ohm +/-10% per IPC-2141A. Impedance coupon required.'

Practical Tips

  • ✓Request actual stackup from fab before design — JLC, PCBWay publish exact Er and layer thicknesses. Generic assumptions cause 5-10% impedance error that may fail controlled impedance spec.
  • ✓Use symmetric stackup (S-G-G-S or S-G-V-G-S) for 4/6-layer boards — balanced copper distribution prevents warpage per IPC-6012D and ensures consistent impedance on both outer layers.
  • ✓Place ground plane adjacent to all signal layers — per Johnson/Graham, this minimizes loop inductance (0.4 nH/mm versus 1.5 nH/mm) and provides 20 dB better EMC performance.

Common Mistakes

  • ✗Using generic FR4 Er=4.5 for all frequencies — Er varies 9% from 1 MHz to 5 GHz. Use frequency-corrected values: Er=4.4 at 1 GHz, 4.2 at 5 GHz per Djordjevic-Sarkar, or specify controlled-Er material for >2 GHz.
  • ✗Placing high-speed signals on layers without adjacent ground reference — signals on L2 with L1 as reference and L3 as power have split return path, increasing EMI by 10-20 dB per Henry Ott.
  • ✗Ignoring copper thickness in impedance calculation — 2oz copper (70um) versus 1oz (35um) shifts impedance by 3-5 ohm due to effective width increase per IPC-2141A.

Frequently Asked Questions

For RF above 2 GHz: Rogers RO4350B (Er=3.48, tan_delta=0.004) or Isola I-Tera (Er=3.45). Lower Er allows wider traces for same impedance, improving manufacturing yield. Low loss tangent reduces attenuation: FR4 loses 0.4-0.6 dB/cm at 5 GHz; Rogers loses 0.1-0.15 dB/cm. Cost premium is 3-5x FR4.
Very — per IPC-2141A, impedance varies as 1/W^0.5 approximately. A 10um width variation on 0.2mm trace shifts impedance by 2.5 ohm (5%). Standard etching tolerance is +/-20um; controlled impedance fabs achieve +/-10um. Always specify width with tolerance: 'W = 0.19 +/-0.01mm'.
Up to 2 GHz with care. FR4 limitations: (1) Er variation +/-8% lot-to-lot; (2) loss tangent 0.02 causes 0.5-1 dB/cm loss at 5 GHz; (3) moisture absorption shifts Er by 2-3%. For >2 GHz or loss-sensitive applications, use Rogers/Isola. FR4 is acceptable for 2.4 GHz WiFi with 10-15mm traces.
Three methods per IPC-TM-650: (1) TDR (time-domain reflectometry) on impedance coupons — most accurate, +/-2%; (2) VNA S-parameter measurement — requires calibration fixtures; (3) Fabrication cross-section measurement of actual geometry. Request TDR report from fab for all controlled impedance boards.
Per Hammerstad-Jensen: Z0 varies approximately as sqrt(H) for microstrip. Doubling dielectric height H increases impedance by 40%. For same 50-ohm target, H=0.2mm needs W=0.38mm; H=0.1mm needs W=0.19mm. Thinner dielectric allows narrower traces (higher density) but requires tighter manufacturing tolerance.

Shop Components

As an Amazon Associate we earn from qualifying purchases.

PCB Manufacturing (JLCPCB)

Affordable PCB fabrication with controlled impedance options

JLCPCB →

FR4 Copper Clad Laminate

FR4 laminate sheets for custom PCB prototyping

Amazon →

Thermal Paste

Thermal interface material for component heat management

Amazon →

Related Calculators

RF

Microstrip Impedance

Calculate microstrip impedance using Hammerstad-Jensen equations. Get Z0, effective dielectric constant, and propagation delay for PCB trace design. Free, instant results.

PCB

Differential Pair

Calculate Zdiff and Zcommon for edge-coupled microstrip pairs. Design USB, HDMI, and Ethernet differential pairs with odd/even mode impedance. Free, instant results.

PCB

Trace Width

Calculate minimum PCB trace width for current capacity per IPC-2221 and IPC-2152. Get resistance, voltage drop, and power dissipation. Free, instant results.

PCB

Trace Resistance

Calculate PCB copper trace DC resistance from width, length, thickness, and temperature. Get sheet resistance and temp coefficient. Free, instant results.