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PCB Via Calculator

Calculate PCB via impedance, capacitance, inductance, and current capacity. Get aspect ratio and DFM warnings for through-hole and blind vias. Free, instant results.

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Formula

Cvia≈0.0554 εr T dD−d pF,Lvia≈0.2h(ln⁡4hd+0.5) nHC_{via} \approx \frac{0.0554\,\varepsilon_r\,T\,d}{D-d}\ \text{pF},\quad L_{via} \approx 0.2h\left(\ln\frac{4h}{d}+0.5\right)\ \text{nH}

Reference: IPC-2141A; Howard Johnson "High-Speed Signal Propagation"

T— Board thickness (mm)
d— Via drill diameter (mm)
D— Pad diameter (mm)
εᵣ— Dielectric constant
h— Via height (= board thickness) (mm)

How It Works

The Via Impedance Calculator computes characteristic impedance, parasitic capacitance, and inductance for PCB vias — essential for high-speed digital design, RF transitions, and signal integrity analysis. Signal integrity engineers use this to minimize via discontinuities that cause 5-15% signal reflection at multi-gigabit data rates.

Per Johnson/Graham's 'High-Speed Digital Design,' via impedance follows Z = 87/sqrt(Er) x ln(1.9 x D/d), where D is antipad diameter, d is via drill diameter, and Er is dielectric constant. A typical 0.3mm via with 0.6mm antipad on FR4 (Er=4.3) has Z approximately 52 ohm — close to 50 ohm target but with 0.3-0.5 pF capacitance and 0.5-1.0 nH inductance that create discontinuity.

Via parasitics scale with board thickness: IPC-2221B shows capacitance C = 1.41 x Er x T x d^2 / (D^2 - d^2) pF, where T is board thickness in mm. A 1.6mm thick board has 2x the capacitance of 0.8mm. This is why HDI stackups with micro-vias (0.1mm drill, 0.15mm pad) are required for >10 Gbps signals — they reduce capacitance by 80% versus standard PTH vias.

For RF applications above 3 GHz, via stub resonance becomes critical. A through-hole via on a signal transitioning at layer 2 of a 1.6mm board has a 1.4mm stub that resonates at approximately 5.5 GHz (quarter-wave), creating a notch in the frequency response. Back-drilling (IPC-6012E) removes the stub, recovering 6-10 dB of insertion loss at resonant frequency.

Worked Example

Problem: Calculate impedance and parasitics for a 0.3mm via (0.25mm finished hole) with 0.6mm antipad on 4-layer 1.6mm FR4 (Er=4.3), signal on L1 transitioning to L3.

Solution per Johnson/Graham:

  1. Via impedance: Z = 87/sqrt(4.3) x ln(1.9 x 0.6/0.3) = 42.0 x ln(3.8) = 42.0 x 1.335 = 56.1 ohm
  2. Via length (L1 to L3): approximately 0.3mm
  3. Capacitance: C = 1.41 x 4.3 x 0.3 x 0.3^2 / (0.6^2 - 0.3^2) = 1.82 x 0.027 / 0.27 = 0.18 pF
  4. Inductance: L = 5.08 x 0.3 x [ln(4 x 0.3/0.3) + 1] = 1.52 x 2.39 = 3.63 nH per mm, so L_total = 1.1 nH
  5. Stub length (below L3): 1.3mm, resonance at f = c/(4 x 1.3mm x sqrt(4.3)) = 5.3 GHz
Result: 56 ohm via with 0.18 pF, 1.1 nH. For 50 ohm line, reflection coefficient = (56-50)/(56+50) = 5.7%. Acceptable for <5 Gbps; back-drill required for 10+ Gbps or signals above 3 GHz.

Practical Tips

  • ✓Use via-in-pad with cap plating for BGA breakout — eliminates trace stub and reduces parasitic inductance by 30% per IPC-7095 recommendations.
  • ✓Add ground vias within lambda/20 (2mm at 10 GHz) of signal vias — provides low-inductance return path, reducing via inductance by 40-60% per Johnson/Graham.
  • ✓For RF/microwave (>6 GHz): specify back-drilling to within 0.1mm of signal layer — removes stub resonance and improves insertion loss by 3-6 dB per via.

Common Mistakes

  • ✗Neglecting antipad size effect — increasing antipad from 0.5mm to 0.8mm raises via impedance by 10-15 ohm, improving match to 50 ohm traces but reducing routing density.
  • ✗Ignoring stub resonance for high-frequency signals — a 1mm stub creates a resonant notch at 7.5 GHz on FR4, causing 10+ dB insertion loss. Always calculate stub frequency for >3 GHz signals.
  • ✗Using PTH vias for 25+ Gbps signals — standard 0.3mm vias have 0.5 pF capacitance; HDI micro-vias (0.1mm) have 0.08 pF, reducing return loss by 6-8 dB per via transition per IEEE 802.3.

Frequently Asked Questions

Via impedance increases with ln(D/d) ratio: larger antipad (D) or smaller drill (d) raises impedance. Per Johnson/Graham, a 0.25mm via with 0.5mm antipad on FR4 gives 48 ohm; with 0.7mm antipad gives 58 ohm. Optimize D/d ratio to match trace impedance — typically D/d = 2.0-2.5 for 50 ohm.
Via discontinuities cause signal reflections: per IEEE 802.3 Ethernet specs, maximum via reflection coefficient is 5% for 10GBASE-T. A 60 ohm via on 50 ohm trace causes 9% reflection — failing spec. At 25 Gbps (100GBASE-CR4), via capacitance >0.3 pF causes 2 dB insertion loss, requiring HDI micro-vias.
Yes — reduce antipad diameter (tighter coupling to ground planes) or increase drill diameter (more copper area). However, smaller antipad risks drill breakout; larger drill reduces routing density. Optimal: use 0.25mm drill with 0.45mm antipad for 45-50 ohm via impedance on FR4 per IPC-2141A guidelines.
Lower Er materials (Rogers RO4350B, Er=3.48) increase via impedance by 10% versus FR4 (Er=4.3) for same geometry. PTFE (Er=2.2) increases impedance by 25%. Capacitance scales with Er, so low-Er materials reduce via capacitance proportionally — beneficial for high-speed signals.
The quasi-static formulas are accurate to +/-10% up to frequencies where via length < lambda/10. For 1.6mm board on FR4, this is approximately 4 GHz. Above 4 GHz, use full-wave EM simulation (HFSS, CST) for accurate S-parameters. Stub resonance effects become dominant above 3 GHz regardless of formula accuracy.

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