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Clock Tree Jitter Budget Calculator

Calculate clock tree timing budget for FPGA and SoC designs. Enter reference oscillator jitter, PLL noise floor, buffer stages, and target clock frequency to compute setup margin.

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Formula

Jtotal=Jref2+Jpll2+N⋅Jbuf2+tskewJ_{total} = \sqrt{J_{ref}^2 + J_{pll}^2 + N \cdot J_{buf}^2} + t_{skew}
J_ref— Reference oscillator jitter (RMS) (ps)
J_pll— PLL additive jitter (RMS) (ps)
J_buf— Per-stage buffer jitter (ps)
N— Number of buffer stages
t_skew— PCB trace skew (deterministic) (ps)

How It Works

This calculator estimates total clock jitter from multiple sources for digital timing analysis. FPGA engineers, high-speed digital designers, and system architects use it to verify timing margins in synchronous systems. Clock jitter directly consumes setup and hold timing budget: T_margin = T_period - T_setup - T_hold - T_jitter_total. Random jitter sources (oscillator phase noise, PLL noise floor, buffer additive jitter) combine as root-sum-of-squares: J_total = sqrt(J1^2 + J2^2 + ...). Deterministic jitter (trace length mismatch, SSO-induced supply bounce) adds linearly per IEEE 1149.11 and Xilinx/Intel timing guidelines. According to JEDEC JESD65C, clock jitter for DDR4 must stay below 3.5% of unit interval (35 ps at 3200 MT/s); for PCIe Gen4, maximum is 3 ps RMS at the receiver. Modern FPGAs specify MMCM/PLL jitter of 50-150 ps RMS per Xilinx UG472 and Intel timing closure documentation.

Worked Example

Problem: Calculate total jitter budget for a 200 MHz FPGA design with external TCXO, on-chip PLL, two clock buffers, and 50 ps trace skew.

Solution - Component specifications:

  1. TCXO (SiTime SiT8008): 50 ps RMS phase jitter (12 kHz - 20 MHz integration)
  2. FPGA MMCM (Xilinx 7-series): 100 ps RMS output jitter per UG472
  3. Clock buffers (TI CDCLVP1102): 25 ps RMS additive jitter each
  4. Trace length mismatch: 50 ps (deterministic, adds linearly)
Random jitter combination (RSS):
  • Two buffers in series: J_buf = sqrt(25^2 + 25^2) = 35.4 ps
  • Total random: J_random = sqrt(50^2 + 100^2 + 35.4^2) = sqrt(2500 + 10000 + 1253) = 117.3 ps
Total jitter (random RSS + deterministic linear):
  • J_total = 117.3 + 50 = 167.3 ps
Timing budget analysis at 200 MHz (5000 ps period):
  • Typical setup time (Xilinx 7-series IOB): 80 ps
  • Typical hold time: 40 ps
  • Available for data path: 5000 - 80 - 40 - 167 = 4713 ps
  • Budget consumed by jitter: 167/5000 = 3.3%
Margin assessment:
  • At 200 MHz with 4.7 ns data path budget, design has comfortable margin
  • Could increase to 500 MHz (2000 ps period) with 1593 ps data path budget
  • At 1 GHz (1000 ps), jitter alone consumes 17% of period - marginal

Practical Tips

  • ✓Budget clock jitter at 2-5% of clock period for conservative timing closure. At 1 GHz (1000 ps period), allow 20-50 ps total jitter. At 200 MHz (5000 ps), 100-250 ps is acceptable. Exceeding 10% jitter consumption typically indicates clock architecture problems requiring redesign rather than optimization per Xilinx UG472.
  • ✓Select clock sources by integrated jitter specification over 12 kHz - 20 MHz bandwidth (standard measurement band per JEDEC). A TCXO with 100 fs jitter in this band contributes negligibly to total budget; an MEMS oscillator with 1-3 ps is adequate for most digital applications; a standard crystal oscillator at 5-10 ps may dominate system jitter.
  • ✓For high-speed SerDes (10+ Gbps), specify reference clock jitter below 1 ps RMS. IEEE 802.3 (Ethernet) and PCIe specifications allocate 3-5 ps total jitter budget at the receiver; half or more is consumed by channel and receiver CDR. Premium oscillators (SiTime Elite Platform, Abracon ASEMB) achieve 100-250 fs jitter for 25G+ applications.
  • ✓Use the Xilinx/Intel timing analyzer jitter reports rather than manual calculation for production designs. Static timing analysis (STA) incorporates PLL jitter models, clock uncertainty, and temperature derating automatically. Manual calculation is valuable for architecture selection and debug, but STA is definitive per FPGA vendor methodology.

Common Mistakes

  • ✗Adding jitter linearly instead of RSS for random sources - linear addition overestimates total jitter by sqrt(N) for N equal sources. Two 100 ps sources combine to 141 ps (RSS), not 200 ps (linear). Use RSS for independent random sources (oscillator noise, PLL noise floor, buffer thermal jitter); add linearly only for deterministic/correlated sources per Xilinx XAPP225.
  • ✗Using peak-to-peak jitter specs directly in RSS calculations - datasheets often specify peak-to-peak jitter (6-sigma envelope for Gaussian). Convert to RMS by dividing by 6 for Gaussian jitter, or by 3 for bounded periodic jitter. Mixing RMS and p-p values without conversion causes 2-6x errors in total jitter estimates.
  • ✗Ignoring PLL bandwidth effect on jitter transfer - a narrow-bandwidth PLL (10-100 kHz) filters reference jitter above its bandwidth but amplifies VCO phase noise below the bandwidth. Wide-bandwidth PLL (1-10 MHz) tracks reference jitter closely. Choose bandwidth based on whether reference or VCO dominates jitter per TI SNAS516.
  • ✗Forgetting power supply noise coupling into PLLs - a 10 mV ripple on PLL analog supply (AVDD) can add 20-100 ps jitter depending on supply rejection ratio (PSRR). Decouple PLL supplies with 10 nF + 100 nF + 10 uF per Xilinx/Intel reference designs. Measure supply noise with oscilloscope (20 MHz+ bandwidth) during debug.

Frequently Asked Questions

Phase noise is frequency-domain representation in dBc/Hz at offset frequencies from carrier; jitter is the time-domain equivalent in seconds RMS or peak-to-peak. Convert using: J_rms = (1/2*pi*f_carrier) * sqrt(2 * integral(10^(L(f)/10) df)) where L(f) is phase noise in dBc/Hz. For quick estimation: -100 dBc/Hz at 100 kHz offset on a 100 MHz clock contributes approximately 1.6 ps RMS jitter from that offset alone. Integration bandwidth matters - specify 12 kHz to 20 MHz per JEDEC for fair comparison.
Per IEEE 802.3ae, maximum total jitter at the 10GBASE-R receiver is 0.28 UI peak-to-peak (28 ps at 10 Gbps). This budget typically splits: 5-10 ps for reference clock jitter, 5-10 ps for transmitter jitter, 10-15 ps for channel ISI and crosstalk, leaving 5-10 ps margin for receiver CDR recovery. Reference clocks for 10GbE must specify jitter below 1 ps RMS integrated over 12 kHz - 20 MHz. 25/100 GbE requirements are proportionally tighter - IEEE 802.3by specifies 0.14 UI for 25 Gbps.

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