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Thermal

Thermal Resistance Network Calculator

Calculate junction, case, and heatsink temperatures through a series thermal resistance network (θJC + θCS + θSA) for component thermal management

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Formula

TJ=TA+PD×(θJC+θCS+θSA)T_J = T_A + P_D × (θ_JC + θ_CS + θ_SA)
T_J— Junction temperature (°C)
T_A— Ambient temperature (°C)
P_D— Power dissipation (W)
θ_JC— Junction-to-case thermal resistance (°C/W)
θ_CS— Case-to-heatsink thermal resistance (°C/W)
θ_SA— Heatsink-to-ambient thermal resistance (°C/W)

How It Works

Thermal resistance network calculator analyzes multi-layer heat flow paths using electrical circuit analogy — essential for PCB thermal analysis, multi-chip module design, and complex enclosure thermal modeling. Thermal engineers, packaging specialists, and reliability engineers use network models to predict temperature distribution and identify thermal bottlenecks. Per JEDEC JESD51-14, thermal resistance R_th = L/(k×A) where L is thickness (m), k is thermal conductivity (W/m·K), and A is cross-sectional area (m²). Series resistances add directly (R_total = R1 + R2 + ...); parallel paths combine as 1/R_total = 1/R1 + 1/R2 + .... Material conductivities: copper 385 W/m·K, aluminum 205 W/m·K, FR4 0.3 W/m·K, silicon 150 W/m·K, thermal grease 1-5 W/m·K, air 0.026 W/m·K.

Worked Example

Model thermal path for QFN-32 package on 4-layer PCB with exposed thermal pad. Layer stack (top to bottom): die (silicon, 0.3mm), die attach (epoxy, 0.025mm), leadframe (copper, 0.2mm), solder (SAC305, 0.1mm), PCB copper (35μm), FR4 (1.5mm), ambient air. Area = 5mm × 5mm = 25mm². Calculate each layer: R_die = 0.3mm/(150×25mm²) = 0.08°C/W. R_attach = 0.025mm/(1.5×25mm²) = 0.67°C/W. R_leadframe = 0.2mm/(385×25mm²) = 0.02°C/W. R_solder = 0.1mm/(50×25mm²) = 0.08°C/W. R_copper = 0.035mm/(385×25mm²) = 0.004°C/W. R_FR4 = 1.5mm/(0.3×25mm²) = 200°C/W (dominates!). Total series: 200.9°C/W. Adding thermal vias (20 vias, 0.3mm diameter, copper-filled): R_vias = 1.5mm/(385×20×π×0.15²mm²) = 0.55°C/W in parallel with FR4. Combined: 1/(1/200 + 1/0.55) = 0.55°C/W — vias reduce thermal resistance 360×.

Practical Tips

  • ✓FR4 thermal conductivity (0.3 W/m·K) is 1000× worse than copper — always provide direct copper path via thermal vias or exposed pad to inner/bottom copper planes
  • ✓Thermal via arrays: 4×4 minimum for meaningful improvement; 8×8 approaches copper-plane conductivity. Via drill 0.3mm, copper-filled provides lowest R_th per IPC-2221B
  • ✓Use JEDEC 2s2p or 1s0p test boards for comparing package θJA — results on actual PCB will differ by 30-50% depending on copper coverage

Common Mistakes

  • ✗Ignoring interface thermal resistance — die attach, solder, and TIM layers contribute 0.5-5°C/W total, comparable to or exceeding bulk material resistance
  • ✗Using 1D model for spreading resistance — heat spreading from small die to large heatsink adds 20-50% to calculated R_th; use spreading resistance formula or FEA
  • ✗Assuming uniform heat generation — hot spots at 2× average power density are common in ICs; local Tj can exceed average by 10-20°C

Frequently Asked Questions

Thermal resistance R_th (°C/W or K/W) is the temperature rise per unit power: ΔT = R_th × P. It is analogous to electrical resistance (V = I × R). R_th = L/(k×A) for conduction through a slab of thickness L, conductivity k, and area A. Lower R_th means better heat transfer. Typical values: 1mm copper (385 W/m·K) at 1cm² = 0.026°C/W; 1mm FR4 (0.3 W/m·K) at 1cm² = 33°C/W.
Direct analogy: temperature ↔ voltage, heat flow ↔ current, thermal resistance ↔ electrical resistance. Kirchhoff's laws apply: series resistances add, parallel resistances combine reciprocally, heat is conserved at nodes. This enables SPICE simulation of thermal networks — model each material as a resistor, heat sources as current sources, ambient as voltage source.
Material conductivity (k): copper = 385 W/m·K, aluminum = 205, silicon = 150, solder = 50, thermal grease = 1-5, FR4 = 0.3, air = 0.026. Geometry: R_th ∝ L/A (thicker = worse, larger area = better). Interfaces: surface roughness and contact pressure affect thermal contact resistance (0.1-1°C/W typical). Spreading: heat spreading from small source to large sink adds resistance.
Series: heat flows sequentially through stacked layers (die → attach → package → TIM → heatsink). Parallel: heat has multiple simultaneous paths (thermal vias in parallel with FR4, convection in parallel with conduction). Real systems combine both: calculate series resistance per path, then combine parallel paths. For complex geometries, use FEA simulation (ANSYS, COMSOL).

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