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Via Thermal Resistance Calculator

Calculate thermal via resistance, array conductance, and current capacity for PCB thermal management. Design filled and plated via arrays. Free, instant results.

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Formula

θvia=h/(kCu×ACu),θarray=θvia/Nθ_via = h / (k_Cu × A_Cu), θ_array = θ_via / N
θ_via— Via thermal resistance (°C/W)
h— Board thickness (m)
k_Cu— Copper thermal conductivity (385 W/mK) (W/mK)
A_Cu— Copper cross-sectional area (m²)
N— Number of vias

How It Works

The Via Thermal Resistance Calculator computes heat transfer capability of copper-plated vias — essential for thermal management of power electronics, LED drivers, and high-power ICs. Thermal engineers use this to design via arrays that achieve junction-to-board thermal resistance below 5-10 C/W, preventing device overheating.

Per IPC-2152 Appendix B, single via thermal resistance follows R_th = L / (k x A), where L is via length (board thickness), k is copper thermal conductivity (385 W/mK), and A is the copper annulus cross-sectional area. A 0.3mm via with 25um plating in 1.6mm board has R_th approximately 150 C/W — far too high for power dissipation. This is why thermal via arrays with 10-50 vias are standard practice.

Via fill dramatically improves thermal performance: unfilled vias conduct heat only through the 25um copper barrel wall; copper-filled vias use the full 0.3mm diameter, reducing thermal resistance by 6-8x per IPC-4761 Type VII. Solder-filled vias (Type V) achieve 70% of copper-fill performance at lower cost.

For QFN/DFN packages with exposed thermal pads, IPC-7093 recommends via pitch of 1.0-1.2mm with 0.3mm drill diameter to achieve 20-30 C/W board-to-ambient thermal resistance. Combined with 2oz inner copper planes, this can reduce junction temperature by 20-40C versus designs without thermal vias — often the difference between reliable operation and thermal shutdown.

Worked Example

Problem: Design thermal via array for 3W LDO in QFN-16 package (5x5mm thermal pad), 4-layer 1.6mm FR4 board, target R_th < 15 C/W from pad to bottom copper pour.

Solution per IPC-7093:

  1. Single via parameters: 0.3mm drill, 25um plating, L = 1.6mm
  2. Annulus area: A = pi x ((0.3/2)^2 - (0.25/2)^2) = pi x (0.0225 - 0.0156) = 0.0217 mm2
  3. Single via R_th: R = 1.6 / (385 x 0.0217e-6) = 191 C/W
  4. Target array R_th: 15 C/W, so need N = 191/15 = 12.7 vias minimum
  5. With 20% margin: N = 16 vias in 4x4 array at 1.0mm pitch (fits 5mm pad)
  6. Verify: 16 parallel vias give R_th = 191/16 = 11.9 C/W
  7. Temperature rise at 3W: deltaT = 3 x 11.9 = 35.8C
Result: 4x4 array of 0.3mm vias achieves 12 C/W. For better performance, use copper-filled vias to achieve 2 C/W with same array.

Practical Tips

  • ✓Use 0.3mm drill with 0.6mm pad for thermal vias — smaller drills have insufficient copper area; larger drills reduce density. This geometry fits 1.0mm pitch per IPC-7093.
  • ✓Specify copper or solder fill for vias under thermal pads — adds $0.10-0.30/board but reduces R_th by 6-8x versus hollow vias per IPC-4761.
  • ✓Connect thermal via array to 2oz internal copper plane — 2oz copper has 2x thermal conductivity of 1oz, enabling 40% better heat spreading per IPC-2152 thermal modeling.

Common Mistakes

  • ✗Using via-in-pad without proper fill specification — unfilled vias under BGA/QFN cause solder wicking and voids, degrading both thermal and electrical performance per IPC-7095.
  • ✗Calculating thermal resistance without accounting for spreading resistance — heat must spread from the via array into copper planes; insufficient plane thickness adds 5-20 C/W per IPC-2152.
  • ✗Ignoring PCB-to-ambient thermal resistance — via arrays only help board-to-junction path; total R_th includes board-to-ambient (typically 20-40 C/W) which often dominates.

Frequently Asked Questions

Larger vias have more copper cross-section and lower thermal resistance. Per IPC-7093: 0.2mm via has R_th approximately 300 C/W; 0.3mm via has approximately 150 C/W; 0.4mm via has approximately 80 C/W (all with 25um plating, 1.6mm board). However, larger vias consume more pad area — balance diameter versus quantity.
Yes — three methods per IPC-4761: (1) Increase via count — N parallel vias have R_th/N; (2) Use copper-fill (Type VII) — reduces single-via R_th by 6-8x; (3) Reduce board thickness — 0.8mm board has half the R_th of 1.6mm. Cost-effective approach: maximize via count first, then add fill if needed.
Copper is optimal with k = 385 W/mK. Copper-filled vias (IPC-4761 Type VII) provide best performance. Solder-filled (Type V, k approximately 50 W/mK) achieves 70% of copper-fill performance. Conductive epoxy fill (k approximately 3-10 W/mK) provides minimal improvement over hollow vias — avoid for thermal applications.
Rule of thumb: 1 via per 0.3W dissipation for hollow vias, 1 via per 2W for copper-filled. For precise calculation: N = (single_via_R_th) / (target_R_th). Example: 150 C/W single via, 10 C/W target = 15 vias minimum. Add 25% margin for manufacturing variation and interface resistance.
Yes — too-tight pitch (<0.8mm) causes thermal shadowing where heat from adjacent vias overlaps, reducing effective conductivity by 15-30%. IPC-7093 recommends 1.0-1.2mm pitch for optimal thermal spreading. Too-wide pitch (>1.5mm) reduces via count in constrained pad areas.

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