Skip to content
RFrftools.io
Thermal

Thermal Via Array Calculator

Calculate thermal resistance of a PCB thermal via array for heat spreading from SMD packages to inner copper planes or heatsinks.

Loading calculator...

Formula

θvia=Lk⋅A,θarray=θviaN\theta_{via} = \frac{L}{k \cdot A}, \quad \theta_{array} = \frac{\theta_{via}}{N}
θ— Thermal resistance (°C/W)
L— PCB thickness (via length) (m)
k— Thermal conductivity (W/m·K)
A— Via cross-sectional area (m²)
N— Number of vias

How It Works

Thermal via array calculator computes PCB vertical thermal resistance for heat extraction from surface-mount power devices — essential for QFN thermal pad design, LED PCB thermal management, and high-power SMD component cooling. PCB designers, thermal engineers, and power electronics designers use via arrays to bypass the poor thermal conductivity of FR4 (0.3 W/m·K vs. copper at 385 W/m·K). Per IPC-2221B, a single 0.3mm diameter copper-plated via (25μm wall) through 1.6mm FR4 has R_th ≈ 70°C/W; copper-filled vias achieve R_th ≈ 30°C/W. Parallel vias reduce total resistance: N vias give R_total = R_single/N. A 5×5 array of copper-filled vias achieves R_th ≈ 1.2°C/W, approaching solid copper performance. Via pitch should be ≥0.8mm (center-to-center) to avoid PCB manufacturing issues.

Worked Example

Design thermal via array for 3W LED on 1.6mm thick FR4 PCB with 6×6mm thermal pad. Target: θSA < 10°C/W to keep junction under 85°C at Ta = 50°C. Single via calculation: dia = 0.3mm, plated wall = 25μm, copper conductivity = 385 W/m·K. Annular area = π×((0.15)² - (0.125)²) = 0.0216mm². R_via = 1.6mm/(385×0.0216mm²) = 192°C/W per plated via. For copper-filled: area = π×(0.15)² = 0.0707mm². R_via = 1.6mm/(385×0.0707mm²) = 59°C/W. Required number: N = 59/10 = 6 copper-filled vias minimum for pad. Arrange in 3×3 array (9 vias) at 2mm pitch within 6×6mm pad: R_total = 59/9 = 6.6°C/W. This exceeds target, providing 34% margin. With bottom-side heatsink (θSA_sink = 5°C/W), total θSA = 6.6 + 5 = 11.6°C/W. Tj = 50 + 3×11.6 = 84.8°C — within 85°C target.

Practical Tips

  • ✓Copper-filled vias cost 30-50% more than standard plated vias but provide 2-3× better thermal performance — cost-effective for power >2W per pad
  • ✓Via-in-pad with planarization allows component placement directly over vias — essential for QFN and BGA thermal pad designs per IPC-7095D
  • ✓Connect via array to internal ground/power planes — planes provide lateral heat spreading, reducing effective θSA by 20-50% vs. isolated via array

Common Mistakes

  • ✗Using plated-only vias instead of filled — plated vias (25μm wall) have 2-3× higher thermal resistance than copper-filled; specify filled vias for thermal applications
  • ✗Spacing vias too closely — via pitch <0.8mm causes PCB delamination risk during reflow; 1mm pitch is recommended per IPC-2221B for thermal via arrays
  • ✗Ignoring solder wicking — unfilled vias can wick solder from thermal pad during assembly, creating voids; use solder mask tenting or via-in-pad with cap plating

Frequently Asked Questions

Rule of thumb: 4 vias minimum for measurable improvement, 16-25 vias approaches solid copper performance. For quantitative sizing: N = R_single_via / R_target. A 1W device targeting θ = 20°C/W needs ~3 copper-filled vias; a 10W device targeting θ = 2°C/W needs ~30 vias. IPC-2152 recommends 1 via per 0.5-1mm² of thermal pad area.
Minimal impact — circular vias are standard and optimally balance thermal performance vs. manufacturing cost. Larger diameter improves thermal resistance (R ∝ 1/area) but reduces routing space. Standard sizes: 0.3mm for signal, 0.4-0.5mm for power, 0.2mm for HDI. Via aspect ratio (depth/diameter) should be <10:1 for reliable plating per IPC-4761.
FR4: 0.3-0.4 W/m·K (through-plane), 0.8-1.0 W/m·K (in-plane due to glass weave). Copper: 385 W/m·K. Aluminum substrate: 1-2 W/m·K for insulated metal substrate (IMS) per Bergquist. Metal-core PCB: 1-8 W/m·K for dielectric, connected to solid aluminum backing (205 W/m·K). For high-power LEDs, IMS or ceramic substrates (AlN: 170 W/m·K) are preferred over FR4.
Copper-filled is preferred for thermal vias — fills entire via barrel with copper, maximizing cross-sectional area. Plated vias have hollow center (25-35μm wall thickness typical), reducing effective area by 60-80%. Cost difference: $0.001-0.005 per via. For via-in-pad under QFN thermal pads, filled and planarized vias are required to prevent solder wicking per J-STD-001H.

Shop Components

As an Amazon Associate we earn from qualifying purchases.

Thermal Paste

Thermal paste and grease for heatsink-to-component bonding

Amazon →

Heatsinks (TO-220)

Aluminum heatsinks for TO-220 and similar packages

Amazon →

Thermal Pads

Silicone thermal pads for PCB component cooling

Amazon →

Related Calculators

Thermal

Junction Temperature

Calculate semiconductor junction temperature from power dissipation and thermal resistance chain (θJC + θCS + θSA). Essential for transistor, MOSFET, and IC thermal design.

Thermal

Heatsink Selection

Calculate the required heatsink thermal resistance (θSA) to keep a device junction below its maximum temperature. Use this to select an appropriate heatsink.

PCB

Via Thermal Resistance

Calculate thermal via resistance, array conductance, and current capacity for PCB thermal management. Design filled and plated via arrays. Free, instant results.

Thermal

Heatsink

Calculate required heatsink thermal resistance and junction temperature for power devices