Predicting Radiated Emissions Before FCC Testing

Pre-Compliance Scanning Is Not Enough on Its Own

Your Raspberry Pi-sized SBC has a 100 MHz processor clock, a 2 cm² power loop between the switching regulator and its bulk capacitor, and a 0.5 m USB cable for the host interface. Your PCB reviewer flagged both during design review. The pre-compliance scan confirmed the concern: harmonics at 300 MHz, 500 MHz, and 700 MHz are within 6 dB of the FCC Part 15 Class B limit at 3 meters.

You have four weeks before the scheduled FCC test. Spinning a new board takes three. You need to know exactly which changes will fix the problem — and which are wasted effort.

Here's the thing most engineers miss: pre-compliance scans tell you there's a problem, but they don't tell you why. Was it the power loop? The USB cable acting as an antenna? Both? Without understanding the underlying mechanisms, you're basically guessing which changes to make. Some teams throw everything at the problem — add ferrites everywhere, tighten every loop, slow down every edge. That works, but it's expensive and time-consuming, and half those changes probably did nothing.

The EMI Radiated Emissions Estimator models both differential-mode (DM) loop radiation and common-mode (CM) cable radiation, applies the spectral envelope of a trapezoidal clock, and runs Monte Carlo over measurement uncertainty to give you a yield figure against the FCC limit. That's the analysis you need to separate the signal from the noise.

Understanding the Two Radiation Mechanisms

Radiated emissions from digital PCBs come from two physically distinct mechanisms, and fixing one does nothing for the other. I've seen teams spend days optimizing their power loop routing only to fail at the test house because the real culprit was CM current on their I/O cables. You need to understand both.

Differential-mode radiation comes from currents circulating in closed loops on the PCB — typically the switching regulator power loop, the decoupling capacitor return path, or a high-speed signal trace paired with its return. Think of it as a tiny loop antenna. The field from a small loop falls off as $1/r^2$ in the near field but transitions to $1/r$ in the far field. The FCC measures at 3 m, firmly in the far field for frequencies above about 16 MHz, so that's the regime we care about.

The electric field from a small DM loop at distance $r$ is approximately:

where $f$ is in Hz, $I$ is the loop current in amps, and $A$ is the loop area in m².

Notice that frequency-squared term. At higher harmonics, even small loops can radiate surprisingly well. But also notice the linear dependence on area — cut your loop area in half, and you cut the field in half. Not squared, just half. That's 6 dB, which sounds like a lot until you realize you were 10 dB over the limit.

Common-mode radiation comes from currents flowing in the same direction on a cable with no differential return. Even microamp CM currents on a half-meter cable create efficient antennas at frequencies where the cable length approaches λ/4. A 0.5 m cable resonates near 150 MHz — squarely in the range of the 100 MHz clock harmonics. This is where things get ugly.

The problem with CM radiation is that it doesn't care how carefully you routed your PCB. The cable is the antenna. You can have perfect ground planes, tight power loops, and beautiful signal integrity, but if you've got even a few microamps of CM current coupled onto that USB cable, you're going to light up the spectrum analyzer at the test house.

Baseline Analysis: The Problem Design

Let's walk through the actual numbers for this design. Enter the following into the EMI Radiated Emissions Estimator:

The tool generates the spectral envelope of the 100 MHz clock with a 1 ns rise time. A trapezoidal waveform has a spectral envelope that rolls off at 20 dB/decade above $1/\pi t_r$, which for a 1 ns rise time is about 318 MHz. Below that corner frequency, odd harmonics (100, 300, 500, 700 MHz…) fall on a relatively flat envelope. Above it, harmonics fall rapidly.

That 1 ns rise time is typical for modern processors running at 100 MHz — nothing exotic. But it means your spectral content extends well beyond the fundamental. The third, fifth, and seventh harmonics all sit below the rolloff corner, so they're all getting hit with roughly the full spectral amplitude.

With the baseline inputs, the tool reports:

• 300 MHz (3rd harmonic): DM estimate 42 dBµV/m, CM estimate 48 dBµV/m, FCC Class B limit 40 dBµV/m. CM exceeds limit by 8 dB.
• 500 MHz (5th harmonic): DM estimate 35 dBµV/m, CM estimate 44 dBµV/m, FCC limit 47 dBµV/m. CM is 3 dB under — but the 95th percentile Monte Carlo result pushes above the limit.
• 700 MHz (7th harmonic): Both sources fall below the limit at 47 dBµV/m.

The CM cable current is the dominant problem at 300 MHz and above. This matches the pre-compliance scan pattern perfectly. You're not borderline at 300 MHz — you're 8 dB over. That's not measurement uncertainty; that's a real problem.

Why the USB Cable Dominates at High Frequencies

At 100 MHz, a 0.5 m cable is λ/6. Not efficient — you're fine there. At 300 MHz, it's λ/2 — a half-wave dipole. Radiation efficiency peaks. At 500 MHz the cable is a full wave, efficiency dips slightly compared to the half-wave case, but 5 µA CM current is still enough to approach the limit.

The DM loop at 2 cm² is not negligible, but the $f^2$ dependence in the field equation works against it: even though it contributes strongly at low harmonics, the small area limits it. The cable, acting as a CM antenna, does not have the same area limitation — it radiates as a dipole, which scales much more favorably with frequency.

This is why adding decoupling capacitors alone will not solve this problem. I've watched teams add ten more 0.1 µF caps to their power rails thinking it'll fix their emissions issues. Decoupling reduces DM loop currents by providing a local charge reservoir and tightening the high-frequency current path. That's great for the DM mechanism. But the CM current on the USB cable comes from parasitic coupling between the board's common-mode noise voltage and the cable shield or ground reference. Decoupling caps do nothing for that. You need a CM choke on the USB lines.

The Fix: Three Targeted Changes

Now we get to the useful part. Instead of randomly trying fixes, we can model exactly what each change does and see if it's worth the effort. Update the tool inputs to reflect the proposed design changes:

Re-run with 100,000 Monte Carlo trials. Results:

• 300 MHz: DM 33 dBµV/m, CM 28 dBµV/m, 95th percentile 36 dBµV/m vs. 40 dBµV/m limit. 4 dB margin.
• 500 MHz: DM 22 dBµV/m, CM 24 dBµV/m, 95th percentile 30 dBµV/m vs. 47 dBµV/m limit. 17 dB margin.
• 700 MHz: Both sources well below limit.

Yield (fraction of MC trials below the FCC limit across all harmonics) goes from 34% to 98%. That's the difference between "we'll probably fail" and "we'll probably pass with margin."

The Monte Carlo analysis is critical here because it accounts for measurement uncertainty, cable positioning variations, and the statistical nature of the test setup. A single-point estimate might show you're 1 dB under the limit, but the 95th percentile could be 3 dB over. The test house doesn't care about your median result — they care about the worst case within their measurement uncertainty.

Implementation Notes

Tightening the power loop from 2 cm² to 0.5 cm² means moving the switching regulator's bulk input capacitor as close as possible to the V_in and GND pins, with a short, wide return path. Reducing loop area by 4× reduces DM field strength by 4× (linear, 12 dB), not 16× — area appears linearly in the field equation, not squared. Still, 12 dB is significant, and it costs you nothing but routing time.

In practice, this means the bulk cap should be right next to the regulator IC, ideally on the same side of the board. I usually aim for less than 5 mm trace length from cap to pin. Use a ground pour for the return path — not a thin trace. The return path area matters just as much as the forward path. Some engineers obsess over the trace from V_in to the cap but then route the ground return halfway across the board. Don't do that.

The CM choke needs to be placed on the USB lines close to the connector, on the PCB side, not the cable side. A 90Ω CM impedance at 100 MHz is sufficient — parts like the TDK ACM2012 or Wurth 742792090 are common choices. One component, inserted in series, reduces CM current by 14 dB in this scenario.

The reason it goes on the PCB side is simple: you want to block CM current before it reaches the cable. If you put the choke on the cable side of the connector, you've already coupled the noise onto the cable, and the choke does nothing. The CM choke presents high impedance to common-mode currents (both D+ and D− moving in the same direction) but low impedance to differential-mode signals (D+ and D− moving in opposite directions). That's exactly what you want — block the noise, pass the signal.

Slowing the rise time from 1 ns to 5 ns shifts the spectral rolloff corner from 318 MHz down to 64 MHz. The 300 MHz harmonic, previously on the flat part of the spectrum, now sits on the −20 dB/decade slope and is attenuated by roughly 14 dB. A 22Ω series resistor in the clock net costs nothing in BOM or board area.

Some designers are nervous about slowing edges because they think it'll cause signal integrity problems. For a 100 MHz clock, a 5 ns rise time is still only 5% of the period — that's perfectly fine. You're nowhere near the point where you'd see setup/hold violations or duty cycle distortion. The processor's input threshold is typically around 1.4V with plenty of hysteresis, so a slightly slower edge doesn't matter. What does matter is cutting your harmonic content by 14 dB at 300 MHz.

All three changes can be implemented with a PCB re-layout and one added component. No hardware re-spin of the processor section is needed. You're not changing the schematic in any fundamental way — just tightening the layout, adding one CM choke, and inserting one series resistor. If you're already respinning the board for other reasons, these changes are basically free. If you're doing a rework to save a production run, the CM choke and series resistor can be hand-soldered in about ten minutes.

EMI Radiated Emissions Estimator