BGA Breakout Width Calculator
Find the widest escape trace that fits between BGA lands from ball pitch, land diameter, your fabricator’s clearance and the number of traces per channel — and whether it fits at all.
Formula
Reference: IPC-7351B land geometry; clearance is a fabricator rule and is supplied as an input; rows per layer from Intel AN 114, "Board Design Guidelines for Intel Programmable Device Packages" (2019.12.31), section 1.3.4.1.
How It Works
Whether a trace can escape between two BGA lands decides how many layers a board needs. If one trace fits, the two outer rows break out on the top layer. If it does not, every row has to fan out to a via and down, and the layer count follows from that.
The arithmetic is the same as any pad-entry problem, but the numbers are tighter. Two adjacent lands leave a channel of the pitch less one land diameter. N traces in that channel need one clearance to each land and one between each adjacent pair, so N+1 clearances. What is left divides between the traces.
Escaping diagonally changes the picture, because the diagonal neighbour sits √2 pitches away rather than one. The channel widens by that factor, which is frequently the difference between fitting and not. The cost is that a diagonal path crosses more of the array, consuming routing space that other escapes wanted.
A single layer breaks out one more row than each channel carries traces. The outermost row routes straight outward with no channel to pass, and each further row needs one more trace through every channel outside it. Intel's AN 114 puts it for one trace between pads: the signals from the first two balls can be routed directly through the first layer. One trace per channel means two rows per layer per side; two means three.
This is why fine-pitch parts drive layer count so hard, and why below a certain pitch the only way out is a via in the land itself — a microvia, and a build-up stack to go with it.
Worked Example
Take a 0.8 mm pitch BGA with 0.4 mm lands and a fabricator minimum clearance of 0.1 mm, escaping orthogonally with one trace per channel.
The channel between adjacent lands is:
0.8 − 0.4 = 0.4 mm
One trace needs a clearance to each land, so two clearances:
(1 + 1) × 0.1 = 0.2 mm
Leaving:
0.4 − 0.2 = 0.2 mm
So a 0.2 mm escape trace fits comfortably — a standard process, no surcharge, and two rows escape per layer: the outer row directly, the next through the channels.
Now tighten the pitch. At 0.5 mm with 0.3 mm lands and the same 0.1 mm clearance, the channel is 0.2 mm and the clearances alone need 0.2 mm. Nothing escapes: the result is refused, and the constraint named is the clearance.
At 0.4 mm pitch with 0.25 mm lands the channel is only 0.15 mm against a 0.2 mm clearance demand — further from fitting still. This is the arithmetic behind the rule of thumb that 0.4 mm pitch parts need vias in pad and a build-up stack: not a preference, just a channel that is narrower than two clearances.
Returning to the 0.8 mm part, switching to a diagonal escape widens the effective pitch to 0.8 × √2 = 1.131 mm and the channel to 0.731 mm, which leaves 0.531 mm for the trace — far more room than the orthogonal route.
Practical Tips
- ✓Do this calculation before choosing the package, not after. It is the input to the layer-count estimate, and layer count is the cost.
- ✓Compare a non-solder-mask-defined land against a solder-mask-defined one — the smaller copper land widens the channel measurably.
- ✓If one trace will not escape, check the diagonal case before concluding you need a build-up stack.
- ✓Where the escape trace comes out under 0.1 mm, get a fabricator quote before committing; below 0.075 mm expect it to be declined or priced as advanced technology.
- ✓Remember that inner rows still need somewhere to go. Escaping N rows per layer means roughly rows-divided-by-N layers of fanout.
- ✓Use the same clearance figure here as in your pad and spacing calculations so the whole footprint is checked against one shop rule.
Common Mistakes
- ✗Sizing the escape trace to the impedance target and only then checking whether it fits. The channel usually decides, and the impedance has to be met another way.
- ✗Forgetting that the second trace in a channel costs an extra clearance as well as its own width.
- ✗Assuming a diagonal escape is free. It fits more easily but crosses more of the array, taking routing room from other nets.
- ✗Using the ball pitch as the channel width. The channel is the pitch less one land diameter.
- ✗Sizing lands from the ball diameter rather than from the footprint. The land is what is on the board, and it is often deliberately smaller than the ball.
- ✗Counting escape rows per layer rather than per layer per side. A peripheral array escapes from four sides; a full array does not escape from the middle at all.
Frequently Asked Questions
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