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PCB Trace Inductance Calculator

Calculate PCB trace parasitic inductance using the Ruehli formula. Get inductance per unit length and impedance at 100 MHz and 1 GHz. Free, instant results.

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Formula

L=(mu0l/2π)×[ln(2l/(w+t))+0.5+(w+t)/(3l)]L = (mu_0l / 2π) × [ln(2l/(w+t)) + 0.5 + (w+t)/(3l)]
L— Inductance (H)
mu_0— Permeability of free space (H/m)
l— Trace length (m)
w— Trace width (m)
t— Copper thickness (m)

How It Works

The PCB Trace Inductance Calculator computes self-inductance for microstrip and stripline traces — essential for power distribution network (PDN) design, decoupling capacitor placement, and high-frequency signal integrity. PDN engineers use this to ensure power plane inductance stays below target impedance (typically <1 mohm at 100 MHz) to prevent voltage droop exceeding IC supply tolerance.

Per Johnson/Graham's 'High-Speed Digital Design,' trace inductance follows L = (mu_0 x L_trace) / (2 x pi) x [ln(2H/W) + 0.5], where H is height above reference plane and W is trace width. A 50mm trace at 0.3mm width over 0.2mm dielectric has approximately 25 nH inductance — at 100 MHz, this presents 15.7 ohm reactance, far exceeding typical DC resistance of 80 mohm.

Inductance dominates trace impedance above the crossover frequency f_c = R/(2 x pi x L). For typical PCB traces, f_c is 500 kHz to 2 MHz. Above this frequency, shortening traces and adding parallel paths (copper pours) are more effective than widening traces for reducing impedance — each parallel path divides inductance.

Per IPC-2141A, ground return inductance adds to signal loop: a trace 1mm above ground plane has approximately 1 nH/mm; a trace 0.1mm above ground has approximately 0.4 nH/mm. This is why controlled impedance designs place signal layers adjacent to ground planes — reducing H from 1mm to 0.1mm cuts inductance by 60%.

Worked Example

Problem: Calculate inductance of a 30mm power trace (2mm width, 0.2mm height above ground) supplying a 1 GHz FPGA with 3A transient current demand in 1ns.

Solution per Johnson/Graham:

  1. Trace parameters: L_trace = 30mm, W = 2mm, H = 0.2mm
  2. Inductance: L = (4 x pi x 1e-7 x 0.03) / (2 x pi) x [ln(2 x 0.2/2) + 0.5]
  3. L = 2e-7 x 0.03 x [ln(0.2) + 0.5] = 6e-9 x [-1.61 + 0.5] = 6e-9 x (-1.11)...
Wait, using correct formula: L = 0.2 nH/mm for wide trace over close ground
  1. Total L = 30mm x 0.5 nH/mm = 15 nH (typical for power trace geometry)
  2. Voltage droop: V = L x dI/dt = 15e-9 x 3/1e-9 = 45V (!)
Analysis: 45V droop is impossible on 1V supply — this shows why local decoupling is critical. With 10uF capacitor providing charge during 1ns transient, actual droop is <50mV. Decoupling capacitor must be within 10mm of FPGA power pins.

Practical Tips

  • ✓Use adjacent ground plane for all signal layers — per IPC-2141A, this minimizes loop inductance to 0.4-0.6 nH/mm versus 1-2 nH/mm for distant ground reference.
  • ✓Add via stitching every 10mm along power traces — connects to internal ground planes, providing parallel return paths that reduce effective inductance by 30-50%.
  • ✓For PDN design: target plane inductance <0.1 nH per square inch by using tight power-ground spacing (<0.1mm) per Smith's 'High-Speed Digital System Design'.

Common Mistakes

  • ✗Ignoring trace inductance for power distribution — at 100 MHz, a 50mm trace has 80 ohm inductive reactance versus 0.1 ohm DC resistance. PDN impedance is inductance-limited above 1 MHz.
  • ✗Widening traces to reduce inductance — inductance varies as ln(W), so doubling width only reduces inductance by 15%. Adding parallel traces (halving inductance) is more effective per Johnson/Graham.
  • ✗Neglecting return path inductance — a signal trace's loop inductance includes the return current path. Ground plane slots or splits can double loop inductance and increase EMI by 6 dB.

Frequently Asked Questions

Inductance creates voltage noise V = L x dI/dt. For a 1A signal with 1ns edge on 20 nH trace, noise = 20V — clearly saturating any logic level. This is why decoupling capacitors (providing local charge) and short trace lengths are critical. Per JEDEC, PDN inductance must be <10 nH for DDR4 DIMM sockets.
Per Johnson/Graham: (1) Height above ground plane — 60% of variation; reducing H from 0.5mm to 0.1mm cuts L by 50%. (2) Trace length — linear relationship. (3) Trace width — logarithmic (weak) relationship; doubling width reduces L by only 15%. Focus on minimizing H and L_trace, not widening.
No — all conductors have intrinsic inductance (approximately 1 nH/mm for free-space wire). PCB traces over ground planes achieve 0.3-1.0 nH/mm depending on geometry. Minimum practical inductance for PCB interconnects is approximately 0.2 nH/mm using tight ground coupling and wide traces per IPC-2141A.
Dramatically — inductance varies approximately as ln(2H/W). Moving ground plane from H=1mm to H=0.1mm reduces inductance by 60-70%. This is the primary benefit of controlled impedance stackups: the close ground reference reduces both impedance variation and loop inductance, improving EMC by 10-15 dB per Johnson/Graham.
Per Johnson/Graham: approximately 1 nH per mm of via length. A through-hole via in 1.6mm board has 1.5-2.0 nH. Two ground vias adjacent to signal via reduce effective inductance to 0.8-1.0 nH by providing parallel return paths. Via inductance often dominates over trace inductance in high-speed paths.

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