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Switching Regulator Output Ripple Calculator

Calculate buck converter output voltage ripple, inductor current ripple, and ESR contribution for switching regulator design

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Formula

ΔIL=(Vin−Vout)×D/(L×f),ΔV≈√(ΔVC2+ΔVESR2)ΔI_L = (V_in − V_out) × D / (L × f), ΔV ≈ √(ΔV_C² + ΔV_ESR²)
D— Duty cycle
L— Inductance (H)
f— Switching frequency (Hz)
C— Output capacitance (F)
ESR— Equivalent series resistance (Ω)

How It Works

The switching regulator ripple calculator determines output voltage ripple, inductor current ripple, and capacitor requirements for SMPS designs — essential for digital load power delivery, mixed-signal systems, and EMC compliance. Power electronics engineers, FPGA designers, and automotive electronics developers use this tool to meet stringent ripple specifications. According to Erickson & Maksimovic's 'Fundamentals of Power Electronics', output voltage ripple has two components: capacitive (ΔVc = ΔIL/(8×fsw×Cout)) and ESR-based (ΔVesr = ΔIL × ESR). For ceramic capacitors with <10 mΩ ESR, capacitive ripple dominates; for aluminum electrolytics with 50-500 mΩ ESR, ESR ripple dominates. TI application note SLVA630 specifies inductor current ripple ΔIL = Vout×(1-D)/(fsw×L), typically targeting 20-40% of DC load current. Modern processors require <10 mV ripple to prevent timing margin degradation — Intel VR14 specifies ±5 mV static tolerance and ±25 mV transient for 1.0 V core rails. Per Murata capacitor application guide, X5R/X7R ceramics lose 50-80% capacitance at rated DC voltage; always derate ceramic capacitor values by 2-3× for ripple calculations.

Worked Example

Design a 12 V to 1.0 V buck converter for FPGA core power at 20 A with <10 mV ripple. Step 1: Set inductor ripple — Target 30% of Iout: ΔIL = 6 A p-p. At 500 kHz, D = 1/12 = 0.0833. L = 1.0×(1-0.0833)/(500k×6) = 305 nH. Use 330 nH (Vishay IHLP-5050). Step 2: Calculate capacitor requirement for 10 mV — Capacitive ripple: Cout_min = 6/(8×500k×0.01) = 150 µF. Step 3: Select capacitors — Use 10×22 µF/6.3V X5R ceramics (220 µF nominal, effective 120 µF after DC bias derating). ESR contribution: 10 paralleled caps = 0.3 mΩ effective. ΔVesr = 6 A × 0.3 mΩ = 1.8 mV. Total ripple = √(8² + 1.8²) ≈ 8.2 mV (within spec). Step 4: Verify transient response — For 15 A load step in 100 ns: ΔV = L×ΔI/Vout = 330 nH × 15/1.0 = 4.95 µs droop time. Add 330 µF bulk capacitor for <50 mV transient.

Practical Tips

  • ✓Per Intel VR design guide, use hybrid output capacitor strategy: MLCCs for high-frequency ripple filtering (<1 MHz), SP-Cap or POSCAP for bulk energy storage and transient response, polymer capacitors for intermediate frequencies
  • ✓Add pi-filter (L-C-L) at output for ultra-low ripple (<1 mV) applications — TI TPS7A8300 post-regulator achieves 15 µV RMS noise after SMPS
  • ✓Place output capacitors within 5 mm of load IC power pins — 10 mm trace length adds 10 nH parasitic inductance, causing 500 mV spike at 50 A/µs load step

Common Mistakes

  • ✗Using nominal ceramic capacitor values — 22 µF/6.3V X5R at 1.0 V DC bias retains only 60-70% (13-15 µF effective); always check manufacturer DC bias curves or use X7R dielectric
  • ✗Ignoring ESR at high frequency — aluminum electrolytic ESR increases 2-5× from 100 Hz to 100 kHz; use datasheet ESR at switching frequency, not 100 Hz catalog value
  • ✗Calculating ripple at nominal conditions only — worst-case ripple occurs at maximum duty cycle (minimum Vin) when inductor current ripple is highest

Frequently Asked Questions

Per TI SLVA630, ripple sources: (1) Inductor current ripple charging/discharging output capacitor — ΔVc = ΔIL/(8×fsw×C), (2) Output capacitor ESR — ΔVesr = ΔIL × ESR, (3) Output capacitor ESL at switching transitions — ΔVesl = ESL × dI/dt. At 500 kHz with ceramic capacitors, capacitive ripple typically contributes 70-80%, ESR 15-25%, ESL 5-10%.
Per Analog Devices AN-1471: (1) Increase switching frequency — doubles fsw halves ripple with same LC values, (2) Increase output capacitance — directly proportional reduction, (3) Use low-ESR capacitors — ceramic MLCCs (2-10 mΩ) versus electrolytic (50-500 mΩ), (4) Increase inductance — reduces ΔIL but slows transient response, (5) Add post-regulator — ferrite bead + capacitor or LDO provides additional 40-60 dB attenuation.
Per industry standards: Digital loads (CPUs, FPGAs): <1% of Vout (10 mV for 1.0 V rail per Intel/AMD VRM specs). Analog/RF circuits: <0.1% (<3 mV for 3.3 V per ADC manufacturer specs). Memory (DDR4/5): ±1.5% per JEDEC standard. Audio: <10 mV to prevent 60 dB SNR degradation. LED drivers: 5-20% acceptable for illumination, <2% for video/photography.
Ripple is inversely proportional to frequency: ΔV ∝ 1/fsw. Doubling frequency from 500 kHz to 1 MHz halves ripple with same LC values, or enables 2× smaller inductor for same ripple. Trade-off: switching losses increase proportionally with frequency. Per TI design guide, optimal frequency balances efficiency (favors lower fsw) against size/ripple (favors higher fsw) — typically 200 kHz-2 MHz for DC-DC converters.
Per Murata and TDK application guides, ranked by ripple performance: (1) MLCC ceramic (2-10 mΩ ESR, best HF performance, but DC bias derating and limited bulk capacitance), (2) Polymer aluminum (8-20 mΩ, good balance), (3) SP-Cap/POSCAP (5-15 mΩ, high capacitance density), (4) Tantalum (50-200 mΩ, surge-rated), (5) Aluminum electrolytic (100-500 mΩ, lowest cost/size for bulk storage, avoid for HF ripple).

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