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PWM Duty Cycle Calculator

Calculate PWM duty cycle, frequency, average voltage, off-time, and RMS voltage from on-time and period parameters

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Formula

D=ton/T×100D = t_on / T × 100%, V_avg = V_cc × D, V_rms = V_cc × √D
D— Duty cycle (%)
t_on— On time (μs)
T— Period (μs)
V_cc— Supply voltage (V)
V_avg— Average voltage (V)
V_rms— RMS voltage (V)

How It Works

The PWM duty cycle calculator determines on-time percentage, average voltage, and power delivery for pulse-width modulated signals — essential for motor speed control, LED dimming, and switching power converters. Embedded developers, motor control engineers, and power electronics designers use this tool to configure timer peripherals and optimize drive circuits. According to TI application note SPRAA88, PWM achieves near-lossless power control by switching fully on/off rather than linear regulation — a 50% duty cycle motor drive dissipates <2% of power in the MOSFET versus 50% in a linear regulator. The fundamental relationship Vavg = Vpp × D (where D = ton/T) provides average voltage seen by the load's mechanical or thermal inertia. Per Microchip AN964, PWM frequency must exceed load time constant by 10× minimum: motor mechanical time constant τ = J×R/K² (typically 10-100 ms) requires fsw > 1 kHz, while LED thermal time constant (~100 ms) allows 100+ Hz for flicker-free dimming. Resolution depends on timer clock and period: an 8-bit timer provides 256 steps (0.4% resolution), while 16-bit timers achieve 65,536 steps (<0.002% resolution).

Worked Example

Design PWM motor speed control for a 12 V DC motor with 500 RPM nominal speed. Requirements: 10-100% speed range, <5% speed ripple, minimum audible noise. Step 1: Calculate target frequency — Motor time constant τ = 50 ms (from datasheet J, R, K). For <5% ripple: fsw > 3/(0.05 × τ) = 1.2 kHz. For inaudible operation: fsw > 20 kHz (above human hearing). Select 25 kHz. Step 2: Determine timer configuration — Using STM32 at 72 MHz: Period = 72M / 25k = 2880 counts. Resolution = 1/2880 = 0.035% (excellent). Step 3: Calculate duty cycle for 50% speed — Assuming linear V-speed relationship: D = 50% for 250 RPM. Vavg = 12 × 0.5 = 6 V. Step 4: Verify MOSFET thermal — At 25 kHz with 20 ns switching time, Qg = 30 nC: Psw = 30n × 12 × 25k = 9 mW. Pcond at 5 A, 10 mΩ: 0.25 W. Total: 0.26 W — no heatsink required for SOT-23 package. Step 5: Add snubber — Motor inductance causes Vspike = L×di/dt. With 100 µH, 5 A turn-off in 50 ns: Vspike = 10 V. Total = 22 V, well within 30 V MOSFET rating.

Practical Tips

  • ✓Per Infineon motor control application note, use center-aligned PWM for reduced EMI — symmetric switching creates 2× effective switching frequency with half the current ripple compared to edge-aligned
  • ✓Implement soft-start ramp (100-500 ms) to prevent mechanical shock and inrush current — linearly increase duty cycle from 0% to target over 10-50 PWM cycles
  • ✓Add RC low-pass filter (fc = fsw/100) after PWM for analog voltage output applications — 25 kHz PWM with 2.5 kHz filter and 10 µF capacitor creates <1% ripple DC voltage

Common Mistakes

  • ✗Using PWM frequency below load bandwidth — a 100 Hz PWM on a motor with 20 ms time constant causes 15-20% speed variation per cycle; increase to 1+ kHz for smooth operation
  • ✗Ignoring deadband at low duty cycles — gate driver propagation delay (10-50 ns) sets minimum effective on-time; at 1 MHz PWM, 50 ns minimum on-time limits resolution to 5% minimum duty cycle
  • ✗Selecting audible PWM frequency (500 Hz - 15 kHz) for motor drives — electromagnetic acoustic noise from motor windings creates annoying whine; use <500 Hz or >18 kHz

Frequently Asked Questions

Per motor and LED driver conventions: 0-100% theoretically possible, but 5-95% practical due to driver limitations. At D < 5%, minimum on-time constraints dominate. At D > 95%, bootstrap capacitor recharge fails in high-side drivers. LED drivers (TI TPS92515) specify 1-100% dimming range with dedicated <1% low-brightness mode. Motor drives typically limit to 10-90% to prevent stall and ensure reliable commutation.
Average power Pavg = Ppeak × D for resistive loads. For inductive loads (motors): power relationship is nonlinear due to back-EMF. At 50% duty cycle, a 12 V/1 A motor draws approximately 0.6 A average (not 0.5 A) due to continuous current mode in the inductance. Per TI DRV8870 datasheet, actual power delivery is Pavg = (Vbus - Vbemf) × Iavg × D + Vbemf × Iavg.
Yes — PWM combined with low-pass filtering creates pseudo-analog output. Per Analog Devices MT-015, an N-bit PWM with fc = fsw/2^N filter achieves N-bit analog resolution. Example: 16-bit PWM at 100 kHz with 1.5 Hz filter creates 16-bit DAC (0.0015% resolution). Limitations: response time inversely proportional to resolution, and noise floor set by filter component tolerance.
Per IEEE 1789 (flicker safety standard): >3 kHz eliminates visible flicker at any duty cycle, >100 Hz acceptable for >10% duty cycle. Human eye detection threshold varies with brightness — at 1% duty cycle, flicker visible up to 2 kHz. Professional video lighting requires >25 kHz to avoid rolling shutter artifacts. Standard LED drivers (TI TPS92200) operate at 200-1000 Hz with proprietary flicker-reduction algorithms.
Resolution = 1/2^N for N-bit timer. Per STM32 application note AN4013: 8-bit = 0.39% steps (256 levels), 10-bit = 0.1% steps (1024 levels), 16-bit = 0.0015% steps (65536 levels). For motor speed control, 8-10 bits sufficient (1% speed accuracy). For precision LED dimming (1000:1 ratio), 10+ bits required. For audio DAC, 16-bit minimum. Higher resolution requires longer timer period or faster clock: 16-bit at 20 kHz needs 1.3 GHz clock or prescaler adjustment.

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