Calculate clock tree timing budget for FPGA and SoC designs. Enter reference oscillator jitter, PLL noise floor, buffer stages, and target clock frequency to compute setup margin.
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Formula
Jtotal=Jref2+Jpll2+N⋅Jbuf2+tskew
J_ref— Reference oscillator jitter (RMS) (ps)
J_pll— PLL additive jitter (RMS) (ps)
J_buf— Per-stage buffer jitter (ps)
N— Number of buffer stages
t_skew— PCB trace skew (deterministic) (ps)
How It Works
<p>Clock jitter is the short-term variation in the timing of clock edges relative to an ideal reference. In digital systems, jitter directly consumes setup and hold time margins. The timing budget available for data propagation is: <strong>T_budget = T_period − T_setup − T_hold</strong>. Total jitter must stay below this budget.</p><p>Jitter sources combine statistically. Independent random jitter sources (oscillator phase noise, PLL noise floor, buffer additive jitter) combine as root-sum-of-squares (RSS). Deterministic jitter sources (PCB trace length mismatch, connector skew) add linearly. This calculator uses RSS for random sources and linear addition for trace skew.</p><p>Clock buffer jitter is typically specified as <em>additive jitter</em> in datasheets (e.g., TI CDCLVP1204: 20 fs RMS). Each buffer stage contributes independently, so N stages contribute √N × J_buf via RSS.</p>
Worked Example
200 MHz FPGA design: Period = 5000 ps. Reference TCXO: 50 ps RMS. Xilinx MMCM: 100 ps RMS. Two CDCLVP1204 buffers: 25 ps × √2 = 35 ps. Trace skew: 20 ps. Total jitter = √(50² + 100² + 35²) + 20 = √(12625) + 20 = 112 + 20 = 132 ps. Available budget = 5000 − 80 (setup) − 40 (hold) = 4880 ps. Setup margin = 4880 − 132 = 4748 ps. Budget used: 2.7%. Plenty of margin — could push clock to 1 GHz before timing becomes critical.
Common Mistakes
✗Adding jitter linearly instead of RSS — this overestimates total jitter by up to 2× for multiple equal sources
✗Forgetting that PLL bandwidth matters — a narrow-bandwidth PLL rejects reference jitter but amplifies VCO phase noise
✗Using peak-to-peak jitter specs instead of RMS for RSS calculation — convert by dividing peak-to-peak by ~6 for Gaussian jitter
✗Ignoring power supply noise coupling into PLLs — a 1 mV ripple on AVDD can add 10s of ps jitter to a sensitive PLL
Frequently Asked Questions
Phase noise is a frequency-domain representation (dBc/Hz at offset frequencies); jitter is its time-domain equivalent. Convert using: J_rms (ps) = (1/2π·f₀) × √(2 × ∫ₒffset S_φ(f) df), where the integral covers the bandwidth of interest. The phase-noise-to-jitter calculator on this site does this conversion directly.
IEEE 802.3ae specifies maximum total jitter of 0.28 UI peak-to-peak at the receiver (28 ps at 10 Gbps). Budget is typically split: ~10 ps for the reference clock, ~8 ps for PCB routing, leaving ~10 ps for the SerDes CDR to recover. This is why 10GbE reference clocks specify sub-1 ps RMS jitter.
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