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PCB DesignAugust 16, 20264 min read

How Much Current Melts a PCB Trace?

Onderdonk's equation was derived for round wire in 1928. Applying it to PCB traces requires knowing the actual cross-section — which isn't rectangular after etching. Here's the physics, the geometry correction, and why the answer is less conservative than you'd hope.

Contents

The scenario

Something has gone wrong. A short, a failed FET, a crowbar event. Current is rising and your trace is the only thing between the fault and the power supply.

Will the trace act as a fuse — opening the circuit before something worse happens — or will it survive long enough for a protection device to trip?

That's a different question from steady-state current capacity (IPC-2152). Steady-state asks how hot the trace runs continuously. Fusing asks how much current, for how long, melts the copper.

Onderdonk's equation

W. H. Onderdonk published this in 1928 for round copper wire, and it's been applied to PCB traces ever since:

I=Aln(TmTa234+Ta+1)33tI = A \sqrt{\frac{\ln\left(\frac{T_m - T_a}{234 + T_a} + 1\right)}{33 \cdot t}}

Where AA is the cross-sectional area in circular mils, TmT_m is the melting point of copper (1083 °C), TaT_a is the ambient temperature, and tt is the time in seconds.

The physics: all the electrical energy goes into heating the conductor (adiabatic assumption — no heat escapes to the substrate). The conductor melts when it reaches 1083 °C.

The adiabatic assumption is conservative for short pulses (under about 1 second) and optimistic for long ones. For a fault that lasts tens of milliseconds, it's quite good — the trace hasn't had time to conduct meaningful heat into the FR4.

The cross-section isn't what you drew

Here's the part that matters for PCB traces and that most implementations get wrong.

You drew a rectangular trace: width WW, thickness tt (determined by copper weight). Area = W×tW \times t. Simple.

But etching doesn't produce vertical sidewalls. The etchant attacks from the top, undercutting as it goes. The result is a trapezoid: full width at the base (substrate side), narrower at the top by twice the undercut.

The etch factor EE is the ratio of vertical etch depth to horizontal undercut. Typical values:

  • Alkaline etch: E3E \approx 3 (good)
  • Acidic cupric chloride: E2.5E \approx 2.5
  • Older or poorly maintained baths: E2E \approx 2

The top width becomes:

Wtop=W2tEW_{top} = W - \frac{2t}{E}

And the actual cross-sectional area is the trapezoid:

A=(W+Wtop)2×t=(WtE)×tA = \frac{(W + W_{top})}{2} \times t = \left(W - \frac{t}{E}\right) \times t

For 2 oz copper (70 µm) on a 0.25 mm trace with E=3E = 3: the rectangular assumption gives 17,500 µm². The trapezoid gives 15,867 µm² — 9.3% less area, which means 4.6% less fusing current.

On fine-pitch traces with heavy copper, the correction is larger. At 1 oz on a 0.15 mm trace: 12% less area.

Time matters enormously

Onderdonk's equation has time under a square root, so fusing current scales as 1/t1/\sqrt{t}. Double the fault duration and the fusing current drops by only 29%.

Put differently: a trace that survives 10 A for 100 ms will fuse at 31.6 A for 1 ms. The same copper, same geometry, vastly different current — because at 1 ms the energy barely begins to diffuse.

This is why fast-acting fuses work: they exploit the adiabatic regime where the I²t product is nearly constant.

For PCB design, the implication is: know your fault duration. A 10 ms crowbar behind a gate driver is a completely different design problem from a sustained short on a power rail.

Ambient temperature shifts the answer more than you'd expect

At 25 °C ambient, the trace needs to rise 1058 °C to melt. At 85 °C ambient (automotive under-hood), it only needs to rise 998 °C — 5.7% less temperature rise, which translates to about 3% less fusing current.

That's not dramatic. But in a design where the trace is already running hot in steady state — say 60 °C above ambient under normal load — the effective starting temperature for a fault is 145 °C, not 85 °C. Now the margin to melt is 938 °C instead of 1058 °C, and fusing current drops by about 6%.

These stack. Hot board, heavy copper running near its IPC limit, fault duration longer than expected. Each shaves a few percent, and together they eat your safety margin.

What Onderdonk doesn't cover

Solder joints. Solder melts at 183–227 °C depending on alloy. Long before the trace melts, the solder joints at both ends open. In practice, a "fused" trace usually means a lifted pad, not a melted conductor. The failure mode is different and the threshold is lower. Delamination. FR4's glass transition is 130–180 °C. Between Tg and copper's melting point there's a long stretch where the laminate is charring, evolving gas, and potentially arcing through carbonised resin. The trace might not melt cleanly — it might carbonise the board first, creating a conductive path that persists after the fault clears. Plated vias. A via's copper wall is typically 25 µm (1 mil), regardless of the surface copper weight. A 0.3 mm drill via has a cross-section of about 25,000 µm² of copper — comparable to a 0.7 mm trace at 1 oz. If your trace fusing calculation assumes the trace is the weakest link but there's a skinnier via in series, the via fuses first.

Design guidance

Don't design the trace as the fuse. PCB traces are poor fuses — they don't open cleanly, they can arc, they can set fire to the laminate. Use a real fuse or an electronic protection device. Do check that the trace survives until protection acts. The useful calculation is: given my protection device's clearing time, does the trace survive? If the answer is no, widen the trace or speed up the protection. For intentional fuse traces (they exist in some safety circuits): use the trapezoid area, design to the hot-ambient case, and add a 2x safety factor on current. Test the actual board — Onderdonk is a model, not a guarantee.

The fusing current calculator applies Onderdonk with the trapezoidal etch correction, lets you sweep fault duration, and reports the I²t product for comparison with upstream protection devices.

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