PCB Stack-Up & Controlled Impedance Guide

Why Stack-Up Design Matters

Here's the thing every high-speed or RF PCB designer runs into: you need to know your layer stack before you can route a single trace. Miss this step and you'll spend weeks debugging signal integrity issues that trace back to a bad impedance target you set on day one. Nail it early and controlled impedance becomes almost automatic—your geometry does the work for you.

I'm going to walk through the physics that actually matters, how to pick materials without blowing your budget, and how to use our PCB Stack-Up Builder to design stacks interactively. No hand-waving, just the models that work.

The Physics: How Trace Geometry Sets Impedance

Think of any PCB trace as a transmission line. Whether it's carrying a 10 MHz SPI clock or a 28 GHz mmWave signal, its characteristic impedance $Z_0$ comes down to four physical parameters:

1. Trace width ($w$) — make it wider and impedance drops
2. Dielectric height ($h$) — the vertical gap between your trace and the nearest ground plane
3. Dielectric constant ($\varepsilon_r$) — higher values pull impedance down
4. Copper thickness ($t$) — has a smaller effect but matters for precise work

These don't combine linearly, which is why you can't just eyeball it. The Hammerstad-Jensen model from 1980 is still the gold standard for closed-form microstrip calculations:

Here $u = w_{\text{eff}} / h$ is your normalized trace width and $\varepsilon_{\text{eff}}$ is the effective dielectric constant—basically a weighted average between your PCB substrate and the air above the trace. This formula holds to within 1% accuracy for $0.1 \leq w/h \leq 10$, which covers almost everything you'll build.

The effective dielectric constant matters because microstrip lives in two worlds: part of the field travels through your FR4 (or Rogers, or whatever), and part travels through air. Stripline, buried between two ground planes, sees only the substrate, so $\varepsilon_{\text{eff}} = \varepsilon_r$ exactly. That difference shows up in your trace widths and your loss budget.

Trace Modes: Microstrip vs. Stripline vs. CPWG

Microstrip

This is your bread-and-butter outer-layer trace: copper on top, ground plane underneath, air (or soldermask) above. The field splits between the dielectric and air, so $\varepsilon_{\text{eff}}$ ends up somewhere between 1 and your substrate's $\varepsilon_r$.

When to use it: Most single-ended signals on outer layers. Digital I/O, moderate-speed clocks, RF traces where you want easy access for probing or tuning. If you're doing SMA launches or need to measure something with a probe, you're probably using microstrip.

Embedded Microstrip

Same geometry but now you've got soldermask on top. That overlay isn't just cosmetic—it raises $\varepsilon_{\text{eff}}$ and drops $Z_0$ by a few ohms. Most engineers skip this correction and then wonder why their bare-board impedance measurements don't match the assembled product. Don't be that engineer.

Stripline

Bury your trace between two solid ground planes and you get stripline. The entire electromagnetic field stays inside the dielectric, so you get $\varepsilon_{\text{eff}} = \varepsilon_r$ with no ambiguity. Better shielding, lower radiation, but you'll need narrower traces to hit the same impedance as microstrip.

When to use it: Inner layers for anything sensitive. DDR4 or DDR5 data groups, PCIe lanes, USB 3.x, or any trace that needs isolation from nearby signals. If crosstalk is your enemy, stripline is your friend.

Asymmetric Stripline

Real PCBs rarely center a trace perfectly between two reference planes—you'd need identical prepreg thicknesses above and below, which adds cost. When the trace sits closer to one plane, the impedance shifts. IPC-2141A gives you a correction factor:

where $h_1$ is the distance to the nearer plane and $b = h_1 + h_2 + t$ is the total dielectric stack height. The asymmetry effect is small—usually a few percent—but it's there.

Differential Pairs

Two traces running complementary signals. The differential impedance $Z_{\text{diff}}$ depends on the single-ended impedance of each trace and how tightly they're coupled. Bring them closer and they start sharing return current, which lowers the differential impedance below $2 Z_0$:

Here $s$ is edge-to-edge spacing and $w$ is trace width. For 100 Ω differential, you typically want 50–55 Ω single-ended traces with spacing roughly equal to the trace width. Tighter coupling pulls you down toward 90 Ω; wider spacing pushes you up toward 110 Ω.

CPWG (Coplanar Waveguide with Ground)

A trace with ground pours on either side on the same layer, plus a ground plane below. The math involves elliptic integrals—nothing you'd want to solve by hand—but CPWG gives you excellent high-frequency performance because the return current stays right next to the signal. Minimal via transitions, tight field confinement, very predictable impedance.

When to use it: mmWave designs, RF connector launch pads (especially SMA), anywhere you need ultra-tight impedance control without dropping down to an inner layer. It eats board real estate but the electrical performance is worth it.

Material Selection

Your dielectric choice sets your baseline impedance and your loss tangent. Here's what actually gets used in production:

For mixed-signal boards—say you've got a 2.4 GHz radio plus a bunch of digital logic—consider a hybrid stack. Put Rogers on the outer layers where your RF lives, use FR4 core for the inner digital routing, and you'll save a ton of money without compromising performance. Most fab houses handle hybrid stacks routinely now.

Loss tangent matters more than people think. That 0.020 tan δ on standard FR4 is fine at 100 MHz but becomes a problem by 1 GHz. You'll see it as insertion loss on a VNA or as your eye diagram closing up on a high-speed serial link. Spend the extra dollar per board on better material if you're anywhere near the edge.

Choosing Your Layer Count

• 2-layer: Fine for hobby stuff and simple circuits. You get one signal layer with decent impedance control if you flood the bottom with ground. Anything beyond basic digital and you'll regret it.

• 4-layer: The sweet spot for most designs. Signal–Ground–Power–Signal gives you two controlled-impedance surfaces, a solid ground reference, and a power distribution plane. If you're doing anything with DDR3, Ethernet, USB 2.0, or moderate-speed clocks, start here.

• 6-layer: Adds two inner signal layers for dense routing. You see this on boards with DDR4 memory interfaces where you need to breakout 64-bit busses without violating length matching rules. The extra layers let you route without cutting up your ground plane.

• 8-layer: Server-grade, networking equipment, complex RF. Gives you room for dedicated RF layers with Rogers material, multiple ground planes for isolation, and enough routing channels to keep high-speed differential pairs away from each other. Costs more but sometimes there's no other way.

DFM Tips

A few things I've learned the hard way:

Keep copper layers symmetric. Odd layer counts cause warping during lamination because one side of the board cools differently than the other. Your fab house can do it but they'll charge you extra and the yield drops. Minimum prepreg thickness is 75 μm for standard processes. You can go thinner with specialized fab but it's not reliable and you'll pay for the privilege. If your impedance calculation wants 50 μm of prepreg, you need to rethink your stack. Specify impedance on your fab drawing. Most shops will adjust trace width by ±10% to hit your target because they know their etch process better than you do. Give them the impedance and the nominal width; let them tweak it. Account for etch factor. Outer layers etch differently than inner layers—the acid attacks from the sides, so you get trapezoidal cross-sections instead of rectangular. Your fab house knows their process; ask for their etch compensation values if you're doing precision RF work. Use the same dielectric material for all layers unless you have a specific reason not to. Mixed-material stacks add cost and lead time because the fab has to do separate lamination cycles. Hybrid stacks (Rogers + FR4) are common enough that most places handle them, but three different materials? You're asking for trouble.

Try It: Interactive Stack-Up Builder

Our PCB Stack-Up Builder gives you a full interactive design environment:

• Drag-and-drop layers to build any stack you want—2L through 8L, symmetric or asymmetric
• Choose from 8 preset stacks ranging from 2L hobby boards to 8L hybrid Rogers configurations
• Pick real materials—FR4 variants, Rogers RO4003C/RO4350B/RO3003, Megtron 6, PTFE
• Compute impedance for all 8 trace modes: microstrip, embedded microstrip, stripline, asymmetric stripline, differential pairs in all those modes, and CPWG
• Solve for trace width given a target impedance—just type in 50 Ω and it'll back-calculate the geometry
• Export CSV for your fab drawing package
• See a live cross-section with proportional layer thicknesses and a trace overlay so you can visualize what you're building

All the math runs in your browser using Hammerstad-Jensen (1980), Cohn (1954), and IPC-2141A formulas. No server round-trip, instant feedback as you adjust parameters. Change the dielectric height and watch the impedance update in real time.

References

• Hammerstad, E. & Jensen, O. "Accurate Models for Microstrip Computer-Aided Design." IEEE MTT-S Digest, 1980.
• Cohn, S.B. "Characteristic Impedance of the Shielded-Strip Transmission Line." Proc. IRE, 1954.
• IPC-2141A. "Design Guide for High-Speed Controlled Impedance Circuit Boards."
• Wadell, B.C. Transmission Line Design Handbook. Artech House, 1991.
• Bogatin, E. Signal and Power Integrity — Simplified. 3rd ed., Pearson, 2018.