PCB

Differential Pair Impedance Calculator

Calculate Zdiff and Zcommon for edge-coupled microstrip pairs. Design USB, HDMI, and Ethernet differential pairs with odd/even mode impedance. Free, instant results.

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Formula Reference

\begin{aligned} Z_0 &= \tfrac{60}{\sqrt{\varepsilon_{eff}}}\ln\!\Big[\tfrac{F(u)}{u} + \sqrt{1 + 4/u^2}\Big] \\ Z_{odd} &= \rho_{odd}\,Z_0\sqrt{\varepsilon_{eff}/\varepsilon_{eff,odd}} \\ Z_{even} &= \rho_{even}\,Z_0\sqrt{\varepsilon_{eff}/\varepsilon_{eff,even}} \\ \varepsilon_{eff,odd} &= 1 + (\varepsilon_{eff} - 1)(1 - f_{odd}) \\ \varepsilon_{eff,even} &= 1 + (\varepsilon_{eff} - 1)(1 + f_{even}) \\ \rho,\ f &= \mathrm{fit}(W/H,\ S/H) \\ Z_{diff} &= 2Z_{odd},\quad Z_{com} = Z_{even}/2 \end{aligned}

Ref: E. Hammerstad and Ø. Jensen, “Accurate Models for Microstrip Computer-Aided Design”, IEEE MTT-S International Microwave Symposium Digest, 1980 (single line); coupling fitted to rftools.io’s 2-D method-of-moments solver (src/lib/pcb/__tests__/solver), within 2% on a mode impedance over W/H 0.2–4 and S/H 0.1–3.

Z₀— Single-ended microstrip impedance (Hammerstad-Jensen) (Ω)

εeff— Single-line effective permittivity (Hammerstad–Jensen)

u— W_eff/H, where W_eff = W + (T/π)(1 + ln(2H/T)) widens the trace for its copper thickness

F(u)— 6 + (2π − 6)·exp[−(30.666/u)^0.7528]

ρ_odd, ρ_even— Each mode’s air-filled impedance as a ratio to the single line, 1 ∓ a·exp[−b·(S/H)^p], with a, b and p fitted to a 2-D method-of-moments solver as functions of W/H; both tend to 1 as the traces separate

f_odd, f_even— Change in each mode’s share of field in the substrate relative to the single line, fitted to the same solver as a function of W/H and S/H; both tend to 0 as the traces separate

Formula

\begin{aligned} Z_0 &= \tfrac{60}{\sqrt{\varepsilon_{eff}}}\ln\!\Big[\tfrac{F(u)}{u} + \sqrt{1 + 4/u^2}\Big] \\ Z_{odd} &= \rho_{odd}\,Z_0\sqrt{\varepsilon_{eff}/\varepsilon_{eff,odd}} \\ Z_{even} &= \rho_{even}\,Z_0\sqrt{\varepsilon_{eff}/\varepsilon_{eff,even}} \\ \varepsilon_{eff,odd} &= 1 + (\varepsilon_{eff} - 1)(1 - f_{odd}) \\ \varepsilon_{eff,even} &= 1 + (\varepsilon_{eff} - 1)(1 + f_{even}) \\ \rho,\ f &= \mathrm{fit}(W/H,\ S/H) \\ Z_{diff} &= 2Z_{odd},\quad Z_{com} = Z_{even}/2 \end{aligned}

Reference: E. Hammerstad and Ø. Jensen, “Accurate Models for Microstrip Computer-Aided Design”, IEEE MTT-S International Microwave Symposium Digest, 1980 (single line); coupling fitted to rftools.io’s 2-D method-of-moments solver (src/lib/pcb/__tests__/solver), within 2% on a mode impedance over W/H 0.2–4 and S/H 0.1–3.

Z₀— Single-ended microstrip impedance (Hammerstad-Jensen) (Ω)

εeff— Single-line effective permittivity (Hammerstad–Jensen)

u— W_eff/H, where W_eff = W + (T/π)(1 + ln(2H/T)) widens the trace for its copper thickness

F(u)— 6 + (2π − 6)·exp[−(30.666/u)^0.7528]

f_odd, f_even— Change in each mode’s share of field in the substrate relative to the single line, fitted to the same solver as a function of W/H and S/H; both tend to 0 as the traces separate

How It Works

The Differential Pair Impedance Calculator computes odd-mode and differential impedance for edge-coupled microstrip traces — essential for USB, HDMI, PCIe, DDR, and Ethernet interfaces. Signal integrity engineers use this to achieve 100-ohm differential impedance (USB/HDMI) or 85-ohm (PCIe Gen3+) with the +/-10% tolerance required by interface specifications.

Differential impedance is twice the odd-mode impedance, $Z_{diff} = 2Z_{odd}$ , and common-mode impedance is half the even-mode impedance, $Z_{com} = Z_{even}/2$ . The calculator starts from the Hammerstad–Jensen impedance of one trace on its own, $Z_0$ , and scales it for each mode by ratios fitted to a two-dimensional method-of-moments field solver. Over trace widths of 0.2 to 4 times the substrate height and spacings of 0.1 to 3 times it, the fit stays within 2% of the solver on a mode impedance. Coupling depends on spacing relative to height, $S/H$ , not only on spacing relative to width. Each mode also has its own effective permittivity: the odd mode drives its field through the air gap between the traces, so it sees less of the substrate than the even mode does. At $W/H = 1.5$ on FR4, $Z_{diff}$ is 14% below $2Z_0$ at $S/H = 1$ and 23% below at $S/H = 0.5$ .

Johnson/Graham's 'High-Speed Digital Design' shows that maintaining constant Zdiff throughout the route is critical: a 15% impedance discontinuity at a via transition causes 7% signal reflection, degrading USB 3.0 eye height by 15-20%. The 3H rule (spacing >= 3x dielectric height) provides -40 dB isolation between differential pairs per IPC-2141A.

For high-speed interfaces, length matching within the pair must be within +/-5 mils (0.127mm) to maintain skew below 1 ps — USB 3.2 Gen 2 (10 Gbps) allows maximum 10 ps intra-pair skew. Propagation delay difference of 6.1 ps/mm on FR4 microstrip means 1.6mm length mismatch violates this spec.

Worked Example

Design a 90 Ω differential pair for USB 3.0 SuperSpeed on a 4-layer FR4 board: 0.2 mm prepreg down to the L2 ground, εr = 4.3, 1 oz copper.

Work in the order the two knobs actually respond. Width sets the single-ended impedance; spacing then trades against it.

Step 1 — width. Solving the surface-microstrip geometry for 50 Ω single-ended gives W = 0.3516 mm, which lands at 49.996 Ω once rounded to four decimals. If the two traces were far apart, the differential impedance would be exactly twice that, 100 Ω.

Step 2 — spacing. Bringing them together lowers the odd-mode impedance. Closing to S = 0.2653 mm gives:

Z_odd = 45.00 Ω, Z_even = 54.63 Ω Z_diff = 2 × 45.00 = 89.99 Ω Z_common = 54.63 / 2 = 27.32 Ω

Step 3 — check the skew. The two modes see different effective permittivities, 3.011 for the odd mode and 3.485 for the even mode, because the odd mode drives its field through the air gap between the traces. That is 0.474 of εeff between them, and it is why a surface pair converts differential energy into common mode over length while a stripline pair does not.

USB 3.0 allows under 5 ps of intra-pair skew. At roughly 5.8 ps/mm for the odd mode, that is about 0.9 mm of permitted length mismatch — match with serpentines and keep the correction close to where the mismatch occurred.

A note on why this example changed. It previously used a coupling term of the form exp(−0.347 · 2S/W), which scales with the spacing-to-width ratio and never references the substrate height at all. Microstrip coupling is governed by spacing relative to height, and on this calculator's own default geometry the old expression reported 55.0 Ω where the correct differential impedance is 100.0 Ω. The model now used is fitted to a committed two-dimensional field solver and collapses onto the single-line result exactly as the pair separates.

Practical Tips

✓Maintain constant trace spacing through entire route including at connectors — even 2mm of wider spacing increases Zdiff by 5-8% and degrades return loss by 3-4 dB.
✓Use ground stitching vias every lambda/10 (15mm at 1 GHz) along differential pairs to maintain reference plane continuity per Johnson/Graham Chapter 6.
✓For USB 3.0/PCIe: specify +/-7% Zdiff tolerance to fab (tighter than standard +/-10%) to ensure interface compliance with margin.

Common Mistakes

✗Neglecting Er variation with frequency — FR4 Er drops from 4.5 to 4.2 between 100 MHz and 5 GHz, shifting Zdiff by 5-7%. Use frequency-corrected values for USB 3.0+ designs.
✗Assuming a linear spacing-impedance relationship. Coupling falls off roughly exponentially with spacing: at $W/H = 1.5$ , doubling the spacing from $S/H = 0.5$ to $S/H = 1$ raises $Z_{diff}$ by only 12%, not 100%.
✗Ignoring via transition discontinuity — standard PTH vias add 0.3-0.5 nH inductance, causing 5-10 ohm impedance spike. Use via-in-pad or back-drilling for >5 Gbps interfaces per IPC-2221B.

Frequently Asked Questions

Why is differential pair impedance important?

Differential signaling provides 6 dB better noise immunity than single-ended (common-mode rejection). Per USB-IF compliance spec, 90-ohm +/-10% Zdiff is mandatory — non-compliant impedance causes >15% eye closure at 5 Gbps and fails USB certification. HDMI 2.1 (48 Gbps) requires +/-7.5% tolerance for reliable 12 Gbps per lane operation.

How does trace spacing affect impedance?

Spacing counts relative to the substrate height, and its effect is far from linear. On this calculator's default geometry (W/H = 1.5, εr = 4.2), Zdiff is 23% below 2·Z₀ at S/H = 0.5, 14% below at S/H = 1, 6% below at S/H = 2 and 3% below at S/H = 3. Wider traces couple slightly less at the same S/H. Beyond S/H = 3 the pair is only loosely coupled, and the geometry is outside the range the model was fitted over, so the calculator flags the result as extrapolated.

Can I use this calculator for all PCB materials?

Yes, for any single homogeneous substrate, within the geometry the model was fitted over. The coupling was fitted to a two-dimensional field solver for trace widths of 0.2 to 4 times the substrate height and spacings of 0.1 to 3 times it, and stays within 2% of the solver on a mode impedance there; outside that range the result is extrapolated and the calculator flags it. The mode permittivities are fitted as ratios to the single line's at εr = 4.3, and those ratios change by under 1.2% across εr from 2.2 to 9.8, inside the same bound. The model is quasi-static and takes one εr, so enter your laminate's value at the frequency you care about. It models neither dispersion nor a soldermask cover.

What impacts differential pair impedance?

Five inputs, with very different weight. Raising each by 10% from this calculator's default geometry moves Zdiff as follows: a wider trace lowers it by 4.7%, a thicker dielectric raises it by 4.0%, a higher dielectric constant lowers it by 4.0%, wider spacing raises it by 1.1% and thicker copper lowers it by 0.5%. A ±10% tolerance on the dielectric height alone therefore moves Zdiff by about 4 to 5% either way, which is why controlled-impedance fabricators measure the pressed stack-up rather than trusting the nominal.

How precise do impedance calculations need to be?

Interface-dependent: USB 2.0 tolerates +/-15% Zdiff; USB 3.0/PCIe Gen3 require +/-10%; PCIe Gen4/5 and USB4 require +/-7%. Per IBIS-AMI simulation data, each 5% impedance error adds 2-3% to bit error rate at 10+ Gbps. For production, add 3% design margin to account for calculation uncertainty plus fab variation.

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