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PCB Controlled Impedance Calculator

Calculate characteristic impedance for surface microstrip, embedded microstrip, and stripline PCB traces. Get Z0, effective Er, and target trace width. Free, instant results.

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Formula

Z0=Z0airεeff,εeffcovered=1+qf(εr−1)+(1−qf) qc(εrc−1),Cstriplineε0εr=4K(k)K(k′)Z_0 = \frac{Z_0^{air}}{\sqrt{\varepsilon_{eff}}},\qquad \varepsilon_{eff}^{covered} = 1 + q_f(\varepsilon_r - 1) + (1-q_f)\,q_c(\varepsilon_{rc} - 1),\qquad \frac{C_{stripline}}{\varepsilon_0\varepsilon_r} = \frac{4K(k)}{K(k')}

Reference: Hammerstad & Jensen, IEEE MTT-S 1980; stripline core verified against the field solver committed in src/lib/pcb/__tests__/solver. The covered-microstrip filling factors are fitted to a layered solve.

Z₀— Characteristic impedance (Ω)
εr— Substrate dielectric constant
εrc— Cover dielectric constant (embedded microstrip)
q_f— Share of the energy already in the substrate
q_c— Share of the remaining energy the cover captures
W— Trace width (mm)
h— Substrate height (mm)
b— Plane-to-plane spacing, 2h for the stripline mode (mm)
t— Copper thickness (mm)
K— Complete elliptic integral of the first kind

How It Works

The Controlled Impedance Calculator computes PCB trace width for target characteristic impedance (50/75/100 ohm) — essential for RF front-ends, high-speed digital interfaces, and signal integrity validation. Hardware engineers and PCB designers use this to prevent signal reflections that degrade eye diagrams by 15-40% when impedance mismatch exceeds 10%.

Per IPC-2141A and Johnson/Graham's 'High-Speed Digital Design,' trace impedance depends on geometry (width W, height H above reference plane) and dielectric constant (Er). The Hammerstad-Jensen equations achieve 1-2% accuracy versus 3D EM simulation for W/H ratios between 0.1 and 10. For a surface microstrip, Z0 increases ~6 ohms per 0.1mm reduction in trace width on standard FR4.

FR4's Er varies from 4.6 at 1 MHz to 4.2 at 5 GHz (Djordjevic-Sarkar dispersion model). This 9% shift changes calculated impedance by 4-5%, which is why Rogers RO4350B (Er = 3.48 +/- 0.05, stable to 10 GHz) is preferred for designs above 2 GHz. Standard fab tolerance is +/-10%; advanced RF fabs achieve +/-5%.

At frequencies where trace length exceeds lambda/10, impedance mismatch causes reflections. A 50-ohm trace driving a 75-ohm load produces 20% reflection coefficient (VSWR 1.5:1, return loss 14 dB). Per Pozar's 'Microwave Engineering,' this reduces power transfer efficiency by 4% and creates standing waves that increase crosstalk by 3-6 dB on adjacent traces.

Worked Example

Design a 50 Ω microstrip for a 2.4 GHz Wi-Fi power amplifier on a 4-layer FR4 board: 0.1 mm prepreg down to the L2 ground, 1 oz copper, εr = 4.3.

Solving the surface-microstrip geometry for 50 Ω gives:

W = 0.1644 mm (6.5 mil), which gives 49.99 Ω at that rounded width εeff = 3.268 propagation delay = 6.026 ps/mm

The effective permittivity is well below the substrate's 4.3 because a surface trace keeps part of its field in the air above it. The same trace buried as a stripline would see the full 4.3 and propagate more slowly — 6.9 ps/mm for the stripline case against 6.0 ps/mm here.

Copper thickness is not a rounding detail at this geometry. The 35 µm of copper widens the trace electrically, and a model that ignores it puts the 50 Ω width around 0.19 mm instead — a 15% error in the dimension you send to the fabricator, all in the direction that lands the board low in impedance.

Tolerance: a typical quick-turn shop quotes ±10% on controlled impedance. At +10% (55 Ω into a 50 Ω system) the VSWR is 1.10:1 and the return loss 26 dB, which is comfortable for most RF work. Note the fabrication drawing as: 'L1 microstrip W = 0.164 mm, Z0 = 50 Ω ±10%'.

Two branches of this calculator changed materially. The embedded-microstrip mode previously used εeff = εr(1 − e^(−1.55·hc/h)), in which the cover's own permittivity never appeared and the effective permittivity fell below 1 for any realistic soldermask — at the default trace width that tripped a guard and the calculator returned a hard 0.00 Ω. The stripline mode used a narrow-trace logarithm that also returned 0 Ω for wide traces. Both now call the shared engine, whose stripline core is the exact conformal-mapping solution.

Practical Tips

  • ✓Verify fab stack-up before design: JLC, PCBWay, OSHPark publish exact Er and layer thicknesses. Generic FR4 assumptions cause 5-10% impedance errors.
  • ✓Add TDR impedance coupon to Gerber package — without it, fab cannot verify compliance and failures are untraceable per IPC-TM-650 2.5.5.7.
  • ✓Use 3W rule (spacing = 3x trace width) between controlled impedance traces to maintain crosstalk below -40 dB per IPC-2141A Section 4.2.6.

Common Mistakes

  • ✗Using 1 MHz Er value (4.6) at GHz frequencies — causes 8-12% impedance error. Always use frequency-corrected Er: 4.4 at 1 GHz, 4.2 at 5 GHz per Djordjevic-Sarkar model.
  • ✗Ignoring copper thickness effect — moving from 0.5oz to 2oz copper shifts impedance by 3-5 ohms due to effective width increase, per IPC-2141A Table 4-1.
  • ✗Routing controlled impedance traces over split ground planes — discontinuity increases impedance by 15-30% and return loss degrades by 6-10 dB (Johnson/Graham Ch. 8).

Frequently Asked Questions

Controlled impedance ensures PCB traces have a specific characteristic impedance (typically 50 ohm for RF, 100 ohm differential for USB/PCIe). Per IPC-2141A, this prevents signal reflections when trace length exceeds lambda/10 — approximately 15mm at 1 GHz on FR4. Uncontrolled impedance causes 15-40% eye diagram degradation in high-speed interfaces.
50 ohms balances power handling (maximum at 30 ohm) and minimum loss (at 77 ohm) per Pozar's derivation. It matches standard RF connectors (SMA, N-type) and test equipment. For coax, 50 ohm provides 86% of maximum power capacity while achieving 93% of minimum attenuation — an optimal engineering compromise adopted by MIL-STD and IEEE standards.
Dielectric constant (Er) directly sets impedance: Z0 is proportional to 1/sqrt(Er_eff). FR4 (Er=4.3) requires 0.19mm trace width for 50 ohm; Rogers RO4350B (Er=3.48) requires 0.24mm. Rogers materials maintain Er within +/-1.5% to 10 GHz versus FR4's +/-8% variation, which is why they are specified for >2 GHz applications per IPC-4101.
Yes — Er decreases 9% from 1 MHz to 5 GHz on FR4 (Djordjevic-Sarkar model), shifting impedance by 4-5%. Additionally, skin effect increases conductor loss from 0.1 dB/cm at 1 GHz to 0.5 dB/cm at 5 GHz, effectively raising impedance by the loss tangent. Use frequency-corrected calculations for designs above 500 MHz.
This calculator uses Hammerstad-Jensen equations (1-2% accuracy per IEEE MTT-S validation). For complex geometries (via transitions, bends, coupled lines), use 2.5D field solvers like Polar SI9000, HyperLynx, or free tools like AppCAD. 3D EM simulation (CST, HFSS) is required for +/-3% tolerance designs per IPC-2141A Appendix A.

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