PDN Impedance: Taming Resonances With Genetic Algorithm

The Problem: A 1.0 V FPGA Rail That Won't Stay Quiet

Modern FPGAs are power-hungry beasts. We're talking 30 A or more from a 1.0 V core rail. The target impedance calculation is straightforward enough:

That's 1.67 milliohms — and you need to hit it across a ridiculously wide frequency range. From below 100 kHz where the VRM is still doing its job, all the way up to 1 GHz where the package decoupling finally kicks in. Everything in between? That's your PCB's power distribution network flying solo. And that's exactly where resonances love to hide and cause trouble.

Let's say you've got a 100 mm × 120 mm board. Standard FR-4 with $\varepsilon_r = 4.3$ and $\tan\delta = 0.02$. Your power and ground planes are separated by a measly 0.1 mm — that's about 4 mils of dielectric. Sounds reasonable, right? Let's plug this into the PDN Impedance Analyzer at rftools.io/tools/pdn-impedance and see what actually happens.

Plane-Pair Cavity Resonances

Here's something most layout guides gloss over: those two parallel copper planes with a thin dielectric between them? They form a resonant cavity. It's basically a rectangular microwave resonator, just really, really flat. The resonant frequencies follow the same physics as any other cavity:

The variables are straightforward — $a$ and $b$ are your board dimensions, $m$ and $n$ are the mode indices (integers starting from zero), and $c$ is the speed of light. For our 100 mm × 120 mm board with FR-4's dielectric constant of 4.3, you get resonances at:

• TM₁₀ mode at 722 MHz
• TM₀₁ mode at 602 MHz
• TM₁₁ mode at 940 MHz

At each of these frequencies, the impedance between your planes shoots up. If any of these spikes poke above your target impedance, the FPGA sees a voltage droop at exactly that frequency. Your high-speed I/O doesn't appreciate that, and you'll start generating spurious EMI that'll make the EMC test house very unhappy.

The Cavity Model: Novak's Green's Function

The analyzer implements Istvan Novak's Green's function approach for modeling this mess. The impedance between two arbitrary points on the plane pair is given by:

Here $d$ is your dielectric thickness, $k_x = m\pi/a$ and $k_y = n\pi/b$ are the spatial wavenumbers, $k = \omega\sqrt{\mu_0 \varepsilon_0 \varepsilon_r}$ is the propagation constant, and $\delta_m$ is the Neumann factor — it's 1 when $m=0$ and 2 otherwise. Same deal for $\delta_n$.

The tool places the probe point at the center of the board. This is worst-case for odd-odd modes and pretty representative of where you'd actually place a BGA.

Why One Capacitor Value Isn't Enough

Every MLCC has a series resonance frequency where its impedance drops to just the ESR. That frequency is determined by the capacitor's own inductance and capacitance:

Take a typical 100 nF 0402 capacitor with about 400 pH of ESL. It'll resonate around 25 MHz. Below that frequency, it behaves like a capacitor and helps reduce your PDN impedance. Above that? It starts looking inductive and actually makes things worse.

To cover the entire 100 kHz to 1 GHz band, you need multiple capacitor values working together. Each one handles a different frequency slice:

The question is: how many of each type? That's where things get interesting, because you're looking at a combinatorial optimization problem with a massive solution space.

The Genetic Algorithm Approach

The analyzer uses a genetic algorithm to find the optimal mix. Each candidate solution is represented as a vector of seven integers — one for each capacitor type — with a constraint that the total can't exceed 30 caps. That's a realistic limit based on the board space you actually have around a typical BGA footprint.

The fitness function works like this: for each candidate solution, the tool calculates the combined impedance of the entire PDN. That's the plane-pair cavity impedance in parallel with all the capacitors (also in parallel). Then it finds the worst-case ratio of $|Z_{PDN}|$ to $Z_{target}$ across the entire frequency range. The GA's job is to minimize that ratio.

Selection uses tournament selection with $k=4$. You grab four random individuals from the population, and whichever one has the best fitness (lowest violation of the target impedance) gets to reproduce. Crossover is two-point crossover on the gene vector. When you create a child, there's a constraint repair step — if the kid ends up with more than 30 total caps, the algorithm randomly trims capacitor counts until you're back under the limit. Mutation gives each gene a chance to get adjusted by $\pm 1$, followed by another round of constraint clamping to keep things legal.

Running the Optimizer

Here's what we fed into the tool:

• Board dimensions: 100 mm × 120 mm, $\varepsilon_r = 4.3$, $\tan\delta = 0.02$
• Plane spacing: 0.1 mm
• Power supply: 1.0 V rail, 30 A load, 5% ripple budget
• VRM characteristics: 0.5 mΩ output resistance, 100 nH loop inductance
• Frequency sweep: 100 kHz to 1 GHz
• Capacitor budget: Maximum of 30 decoupling caps

We ran the GA with a population of 400 individuals over 400 generations. The results were pretty enlightening.

Impedance Profile

The bare plane-pair impedance without any decoupling shows massive spikes at each cavity resonance — exactly what the math predicted. Add the optimized set of 30 capacitors, and those spikes get crushed down below the 1.67 mΩ target across the entire frequency range. The worst violation ended up being −0.5 dB below target, which means we actually have some margin to work with.

Optimized Capacitor Mix

After 400 generations, the GA settled on this solution:

Look at that distribution. The heaviest allocation — eight caps — goes to 100 nF. That's your mid-band workhorse frequency. The 10 nF and 1 µF values each get five or six to cover the transition zones where impedance would otherwise peak. The extreme values at both ends (100 µF and 100 pF) only need two each. Just enough to anchor the frequency band without wasting precious board real estate.

GA Convergence Behavior

The fitness metric (worst-case $|Z_{PDN}|/Z_{target}$ ratio) started around 2.5 in the first generation. By generation 150, it had dropped to about 0.85 and pretty much stayed there. This tells you the GA found a near-optimal solution well before hitting the 400-generation limit. You could probably get away with running just 200 generations for a board this size and save some computation time.

Design Insights That Actually Matter

1. Plane Spacing Matters More Than You Think

Cut your plane-pair spacing from 0.2 mm to 0.1 mm and you roughly double the interplane capacitance. Remember, $C = \varepsilon_0 \varepsilon_r A / d$ — capacitance is inversely proportional to spacing. This shifts where your cavity resonances occur and can eliminate the need for two or three decoupling caps. If your stackup can handle tighter plane spacing, that's probably the cheapest PDN improvement you can make. Most engineers skip this optimization and regret it later when they're trying to squeeze in more caps.

2. ESL Dominates Above 100 MHz

Once you're above the series resonant frequency, a capacitor stops acting like a capacitor. It looks inductive. The ESL — not the capacitance value — determines what happens at high frequencies. That's why the optimizer strongly prefers 0201 packages for anything above 100 MHz. They've got 200-300 pH of ESL compared to 400-800 pH for 0402 or 0603 packages. That difference is everything when you're trying to hit a 1.67 mΩ target at 500 MHz.

3. Don't Ignore the VRM Loop Inductance

Your voltage regulator module has output inductance — typically labeled $L_{VRM}$ in datasheets. This creates an impedance rise at low frequencies that no amount of bulk capacitance can completely fix. If $L_{VRM}$ is too high, you'll have a gap between where the VRM's control bandwidth ends and where your decoupling network starts doing useful work. The analyzer models this as a series RL coming from the VRM, and it matters more than most people realize.

4. The 30-Cap Constraint Is Actually Realistic

With a typical 15 mm × 15 mm BGA footprint, you can physically fit maybe 30 to 40 decoupling caps in a 5 mm halo around the package. Any more than that and you're either overlapping caps or pushing them so far away that their inductance kills their effectiveness. The constraint forces the optimizer to make intelligent tradeoffs instead of just brute-forcing the problem with hundreds of capacitors.

Comparing With a Hand-Picked Solution

There's a common rule of thumb that says to use ten 100 nF caps, five 10 µF caps, and five 1 µF caps. That's 20 capacitors total. Run that through the analyzer and you'll see it completely falls apart above 200 MHz because there's no high-frequency coverage. Add five 10 nF caps and you fix the 200-500 MHz range, but the 500 MHz to 1 GHz region still has resonance spikes poking above your target impedance.

The GA's solution uses all seven capacitor values and allocates the count based on where the impedance profile actually needs help. No rule of thumb can match that level of frequency-domain awareness. It's like the difference between mixing paint by eye versus using a spectrophotometer.

Practical Notes You Should Know

Board size sensitivity matters. Larger boards have lower-frequency cavity resonances. A 200 mm × 250 mm server motherboard might see its TM₁₀ mode at 290 MHz — right in the middle of your decoupling band where it's a real problem. Smaller boards like 50 mm × 50 mm push those resonances above 1 GHz where they're much less of a headache. Dielectric constant affects everything. High-$\varepsilon_r$ laminates like Rogers or Megtron lower your resonant frequencies. This is usually beneficial because you get more interplane capacitance, but it can surprise you if resonances suddenly shift into your signal bandwidth. FR-4 at 4.3 is pretty middle-of-the-road, which is why it's so popular. Loss tangent provides damping. FR-4's $\tan\delta$ of about 0.02 gives you modest damping of those resonance peaks. Switch to a low-loss laminate with $\tan\delta$ around 0.002 and you'll see much sharper resonance spikes that are harder to suppress with decoupling. Sometimes a little loss is your friend.

Wrapping Up

PDN design is fundamentally a frequency-domain problem that spans four decades of bandwidth. Those plane-pair cavity resonances create impedance spikes that hand-placed decoupling strategies almost always miss. The genetic algorithm approach finds a capacitor mix that actually covers the full frequency band while respecting realistic constraints on how many caps you can physically place.

You can try the tool yourself at rftools.io/tools/pdn-impedance. Plug in your board dimensions, stackup parameters, and power requirements, then let the optimizer figure out the decoupling solution. It'll probably find something better than whatever rule of thumb you were planning to use.

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Related tools: PCB Trace Impedance, Via Impedance, Decoupling Capacitor, Bypass Cap Resonance