PDN Impedance: Taming Resonances With Genetic Algorithm

The Problem: A 1.0 V FPGA Rail That Won't Stay Quiet

Modern FPGAs are power-hungry beasts. We're talking 30 A or more from a 1.0 V core rail. The target impedance calculation is straightforward enough:

That's 1.67 milliohms — and you need to hit it across a ridiculously wide frequency range. From below 100 kHz where the VRM is still doing its job, all the way up to 1 GHz where the package decoupling finally kicks in. Everything in between? That's your PCB's power distribution network flying solo. And that's exactly where resonances love to hide and cause trouble.

Let's say you've got a 100 mm × 120 mm board. Standard FR-4 with $\varepsilon_r = 4.3$ and $\tan\delta = 0.02$. Your power and ground planes are separated by a measly 0.1 mm — that's about 4 mils of dielectric. Sounds reasonable, right? Let's plug this into the PDN Impedance Analyzer at rftools.io/tools/pdn-impedance and see what actually happens.

Plane-Pair Cavity Resonances

Here's something most layout guides gloss over: those two parallel copper planes with a thin dielectric between them? They form a resonant cavity. It's basically a rectangular microwave resonator, just really, really flat. The resonant frequencies follow the same physics as any other cavity:

The variables are straightforward — $a$ and $b$ are your board dimensions, $m$ and $n$ are the mode indices (integers starting from zero), and $c$ is the speed of light. For our 100 mm × 120 mm board with FR-4's dielectric constant of 4.3, you get resonances at:

• TM₁₀ mode at 723 MHz
• TM₀₁ mode at 602 MHz
• TM₁₁ mode at 941 MHz

At each of these frequencies, the impedance between your planes shoots up. If any of these spikes poke above your target impedance, the FPGA sees a voltage droop at exactly that frequency. Your high-speed I/O doesn't appreciate that, and you'll start generating spurious EMI that'll make the EMC test house very unhappy.

The Cavity Model: Novak's Green's Function

The analyzer implements Istvan Novak's Green's function approach for modeling this mess. The impedance between two arbitrary points on the plane pair is given by:

Here $d$ is your dielectric thickness, $k_x = m\pi/a$ and $k_y = n\pi/b$ are the spatial wavenumbers, $k = \omega\sqrt{\mu_0 \varepsilon_0 \varepsilon_r}$ is the propagation constant, and $\delta_m$ is the Neumann factor — it's 1 when $m=0$ and 2 otherwise. Same deal for $\delta_n$. The analyzer evaluates the sum at a single port, where the IC draws its current ($x_1 = x_2$, $y_1 = y_2$), and gives that port a size: a square set by the port size input, 1 mm by default, over which each cosine is averaged. A point port's sum never converges, because the 2-D Green's function is singular at the source, so its answer would depend on where the sum was cut off. With a finite port it converges, and below the first mode the result no longer depends on how far up you sweep.

By default the tool places the port at the board's one-third point, $(a/3, b/3)$, which is (33.3 mm, 40 mm) on this board, and the choice is deliberate. Each mode's voltage goes as $\cos(m\pi x/a)\cos(n\pi y/b)$, so at the center every mode with an odd $m$ or an odd $n$ has a null: TM₁₀, TM₀₁ and TM₁₁ all vanish there. Only even-even modes such as TM₂₀, TM₀₂ and TM₂₂ peak at the center, and on this board the first of them, TM₀₂, is at 1205 MHz, above the sweep. A corner, by contrast, is a voltage maximum of every mode. At a one-third point, $\cos(m\pi/3)$ is never zero, so no mode has a null there: each couples at least 1/16 as strongly as at a corner, and the tool lists each mode's coupling beside it, 0.25 for TM₀₁ and TM₁₀ and 0.063 for TM₁₁ here. The default is still a stand-in for your layout: set the port X and Y location to where the BGA actually sits, and check a point near a corner for the worst case.

Why One Capacitor Value Isn't Enough

Every MLCC has a series resonance frequency where its impedance drops to just the ESR. That frequency is determined by the capacitor's own inductance and capacitance:

Take a typical 100 nF 0402 capacitor with about 400 pH of ESL. It'll resonate around 25 MHz. Below that frequency, it behaves like a capacitor and helps reduce your PDN impedance. Above that? It starts looking inductive and actually makes things worse.

To cover the entire 100 kHz to 1 GHz band, you need multiple capacitor values working together. The analyzer's library has seven, each handling a different frequency slice:

The question is: how many of each type? That's where things get interesting, because you're looking at a combinatorial optimization problem with a massive solution space.

The Genetic Algorithm Approach

The analyzer uses a genetic algorithm to find the optimal mix. Each candidate solution is represented as a vector of seven integers — one for each capacitor type — with a constraint that the total can't exceed 30 caps. That's a realistic limit based on the board space you actually have around a typical BGA footprint.

The fitness function works like this: for each candidate solution, the tool calculates the combined impedance of the entire PDN. That's the plane-pair cavity impedance in parallel with all the capacitors and the regulator. Then it finds the worst-case ratio of $|Z_{PDN}|$ to $Z_{target}$ across the decoupling band, which runs from the bottom of the sweep to 80 % of the first cavity resonance: 100 kHz to 482 MHz on this board, where TM₀₁ is at 602 MHz. The GA's job is to minimize that ratio: with a flat target, the worst point anywhere in the band sets the droop. Designs within 0.1 dB of the lowest ratio count as tied, and among them the tool picks the one that keeps the rest of the band closest to the target where the budget can reach it, and closest to the floor, the lowest impedance any design within the budget achieves, where it cannot. Frequencies in that band where no design within the budget can reach the target are reported as unreachable, with their floor, and they count against the verdict.

Selection uses tournament selection with $k=4$. You grab four random individuals from the population, and whichever one has the best fitness (lowest violation of the target impedance) gets to reproduce. Crossover is two-point crossover on the gene vector. When you create a child, there's a constraint repair step — if the kid ends up with more than 30 total caps, the algorithm randomly trims capacitor counts until you're back under the limit. Mutation gives each gene a chance to get adjusted by $\pm 1$, followed by another round of constraint clamping to keep things legal. Seeding and refinement bracket the GA. A tenth of the first population is built greedily, adding one capacitor at a time wherever it lowers the worst case most. After the last generation, the best designs the search ever evaluated are refined one move at a time (add, remove or swap one capacitor), judged on the same two-stage ranking with the true worst case, which the tool finds between grid points rather than reading it off them, until no single move improves the ranking. That is why different random seeds land on the same design.

Running the Optimizer

Here's what we fed into the tool:

• Board dimensions: 100 mm × 120 mm, $\varepsilon_r = 4.3$, $\tan\delta = 0.02$
• Plane spacing: 0.1 mm
• Power supply: 1.0 V rail, 30 A load, 5% ripple budget, so a 1.67 mΩ target
• VRM characteristics: 0.5 mΩ output resistance (DCR) and the default 100 kHz loop bandwidth, from which the tool derives 0.8 nH of output inductance; board inductance at its 1 nH default
• Port: left blank, so the tool places it at the one-third point, (33.3 mm, 40 mm), with the default 1 mm port size
• Frequency sweep: 100 kHz to 1 GHz
• Capacitor budget: Maximum of 30 decoupling caps

We ran it on the free lane, where the GA has a population of 200 individuals over 150 generations (the paid lane runs 400 over 400). The results were pretty enlightening.

Impedance Profile

Seen from the default port, the bare plane-pair impedance without any decoupling shows a spike at each of the three cavity resonances, exactly what the math predicted, and a far larger one near 54 MHz, where the 1.8 nH feed path resonates with the planes' 4.6 nF. Add the optimized set of 30 capacitors, and the tool's verdict is blunt: target not met across 100 kHz–482 MHz. The worst case is 62.19 mΩ at 208 MHz, +31.42 dB over the target: an anti-resonance, where the 10 nF parts, inductive above their 85 MHz SRF, resonate with the 1 nF parts and the planes, both still capacitive there, the planes up to their series resonance near 240 MHz. Above about 140 kHz the profile sits over the target everywhere in the band, with lower peaks of 17 mΩ near 1 MHz, where the bulk capacitance resonates with the feed path, and 39 mΩ near 18 MHz.

Against the bare board, that is a large improvement where the board was worst: its 47 Ω at 54 MHz drops to 13 mΩ, and the design's worst case is more than 57 dB below it. It is not lower everywhere, though. At 208 MHz the bare board reads 45 mΩ, and near 1 MHz 11.6 mΩ against the design's 16.6 mΩ: adding capacitance creates anti-resonances as well as removing them. The tool also says why the target is out of reach: from 16 MHz to the band's edge, apart from two narrow windows, it marks the band unreachable, because no design of 30 parts from its library gets below 1.672 to 2.151 mΩ there. No mix can meet the target at those frequencies. Those floors are close to the target, but each is the best any 30 parts can do at one frequency on its own; one design has to cover the whole band at once, and the best one the tool finds peaks at 62.19 mΩ. The resonance spikes above the band remain: at those frequencies the capacitors are inductive, so decoupling cannot remove them. Plane damping, capacitors placed where a mode's voltage is large (not on its nulls) and edge treatment are what control them; the analyzer lumps every capacitor at the port, so placement is outside what it models.

Optimized Capacitor Mix

After 150 generations and the refinement that follows, the GA settled on this solution, and three different random seeds return the same one:

Look at that distribution. Twenty-seven of the thirty parts are 10 nF and 1 nF, the lowest-ESL values in the library. With a flat target the worst point in the band sets the droop, so the optimizer ranks designs on it first, and on this board that point is the anti-resonance above 200 MHz: holding it down takes low-ESL parts in numbers. The bulk end gets one each of 10 µF, 1 µF and 100 nF, with no 47 µF or 100 µF part at all, and the rest of the band stays below the peak. The target is still not met, and the unreachable ranges say why: above 16 MHz, apart from two narrow windows, no 30 parts from the library reach the target, whatever the mix. The budget, not the mix, is the problem.

GA Convergence Behavior

The fitness metric (the worst-case $|Z_{PDN}|/Z_{target}$ ratio on the frequency grid, across the whole band) started at 37.46 in the first generation, which already holds the greedy seeds. By generation 4 it had dropped to 37.13, and it never moved again. The verdict's 62.19 mΩ is 37.24 times the target, a little higher, because the tool refines the peak between grid points. This tells you the GA found its answer well before the 150-generation limit, and that the answer is far above 1. The levers are more capacitors or a less demanding target.

Design Insights That Actually Matter

1. Plane Spacing Matters More Than You Think

Cut your plane-pair spacing from 0.2 mm to 0.1 mm and you roughly double the interplane capacitance. Remember, $C = \varepsilon_0 \varepsilon_r A / d$ — capacitance is inversely proportional to spacing. What spacing does not do is move your cavity resonances: $d$ does not appear in $f_{mn}$, which depends only on the board dimensions and $\varepsilon_r$. Spacing sets how tall the peaks are. Halving $d$ halves the spreading inductance and with it the plane pair's impedance, peaks included, and the thinner dielectric adds conductor loss, which lowers the Q and damps the peaks further. That can eliminate the need for two or three decoupling caps. If your stackup can handle tighter plane spacing, that's probably the cheapest PDN improvement you can make. Most engineers skip this optimization and regret it later when they're trying to squeeze in more caps.

2. ESL Dominates Above 100 MHz

Once you're above the series resonant frequency, a capacitor stops acting like a capacitor. It looks inductive. The ESL, not the capacitance value, determines what happens at high frequencies. That's why the optimizer spends most of the budget on the lowest-ESL parts in its library: 27 of the 30 capacitors above are 10 nF and 1 nF 0402s, at 350 and 300 pH, against 600 to 1200 pH for the 0603 to 1206 bulk parts, and at 200 capacitors it picks 129 of the 10 nF and 57 of the 1 nF. That difference is everything when you're trying to hit a 1.67 mΩ target at 400 MHz.

3. Don't Ignore the VRM Loop Inductance

Your voltage regulator module has output inductance — typically labeled $L_{VRM}$ in datasheets. This creates an impedance rise at low frequencies that no amount of bulk capacitance can completely fix. If $L_{VRM}$ is too high, you'll have a gap between where the VRM's control bandwidth ends and where your decoupling network starts doing useful work. The analyzer models this as a series RL coming from the VRM, with $L_{VRM} = R_{DC}/(2\pi f_{BW})$ derived from the DCR and the loop bandwidth (0.8 nH for this rail), plus a board inductance in series with it for the path from the regulator to the planes, an input that defaults to 1 nH. It matters more than most people realize.

4. The 30-Cap Constraint Is Actually Realistic

With a typical 15 mm × 15 mm BGA footprint, you can physically fit maybe 30 to 40 decoupling caps in a 5 mm halo around the package. Any more than that and you're either overlapping caps or pushing them so far away that their inductance kills their effectiveness. The constraint forces the optimizer to make intelligent tradeoffs instead of just brute-forcing the problem with hundreds of capacitors. The tool also tells you when a target is beyond what the board alone can do. Rerun this rail with 200 capacitors and it still fails, with a worst case of 7.3 mΩ at 232 MHz and 186–214 MHz and 392–482 MHz still unreachable. At 1.67 mΩ, the top of the band belongs to the package and die capacitance.

Comparing With a Hand-Picked Solution

There's a common rule of thumb that says to use ten 100 nF caps, five 10 µF caps, and five 1 µF caps. That's 20 capacitors total, and none of them resonates above the 100 nF's 25 MHz. The analyzer doesn't score a fixed mix, but it bounds every mix of 20: run it with a 20-capacitor budget and it marks 10 MHz to 482 MHz unreachable, apart from a narrow window at the planes' series resonance, because no 20 parts from its library get below 1.677 mΩ anywhere in that range. So the rule of thumb fails there before you even run it. Add five 10 nF caps and the 25-capacitor run only moves the start of that range up to 13 MHz.

The GA's solution uses five of the seven capacitor values and allocates the count to hold down the worst point of the impedance profile. No rule of thumb can match that level of frequency-domain awareness. It's like the difference between mixing paint by eye versus using a spectrophotometer.

Practical Notes You Should Know

Board size sensitivity matters. Larger boards have lower-frequency cavity resonances. On the same FR-4, a 200 mm × 250 mm server motherboard has its lowest mode, TM₀₁ along the 250 mm side, at 289 MHz — right in the middle of your decoupling band where it's a real problem. Smaller boards like 50 mm × 50 mm push those resonances above 1 GHz where they're much less of a headache. Dielectric constant affects everything. Every mode frequency scales as $1/\sqrt{\varepsilon_r}$, and the plane capacitance scales with $\varepsilon_r$. Low-loss laminates such as Rogers RO4350B ($\varepsilon_r = 3.48$) and Megtron 6 (about 3.4 to 3.7) have a lower $\varepsilon_r$ than FR-4 (about 4.2 to 4.6), so switching to one raises your resonant frequencies, by about 11% going from 4.3 to 3.48, and cuts the interplane capacitance in proportion. To pull the modes down, the levers are a higher-$\varepsilon_r$ dielectric, such as the thin embedded-capacitance laminates made for plane pairs, or larger planes. Either way, check where the modes land before you change material. FR-4 at 4.3 is pretty middle-of-the-road, which is why it's so popular. Loss tangent provides damping. FR-4's $\tan\delta$ of about 0.02 gives you modest damping of those resonance peaks. Switch to a low-loss laminate with $\tan\delta$ around 0.002 and you'll see much sharper resonance spikes that are harder to suppress with decoupling. Sometimes a little loss is your friend.

Wrapping Up

PDN design is fundamentally a frequency-domain problem that spans four decades of bandwidth. Those plane-pair cavity resonances create impedance spikes that hand-placed decoupling strategies almost always miss. The genetic algorithm approach finds the best capacitor mix it can for the band below the first cavity mode while respecting realistic constraints on how many caps you can physically place, and when no mix within that count can meet the target, the tool tells you where and by how much instead of hiding it.

You can try the tool yourself at rftools.io/tools/pdn-impedance. Plug in your board dimensions, stackup parameters, and power requirements, then let the optimizer figure out the decoupling solution. It'll probably find something better than whatever rule of thumb you were planning to use.

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Related tools: PCB Trace Impedance, Via Impedance, Decoupling Capacitor, Bypass Cap Resonance