PCB

PCB Via Calculator

Calculate PCB via impedance, capacitance, inductance, and current capacity. Get aspect ratio and DFM warnings for through-hole and blind vias. Free, instant results.

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Formula

C_{via} \approx \frac{0.0554\,\varepsilon_r\,T\,D}{D_a-D}\ \text{pF},\quad Z_{via} \approx \frac{60}{\sqrt{\varepsilon_r}}\ln\frac{D_a}{d},\quad L_{via} \approx 0.2h\left(\ln\frac{4h}{d}+0.5\right)\ \text{nH}

Reference: IPC-2141A; IPC-2221B; Howard Johnson "High-Speed Signal Propagation"

T— Board thickness (mm)

d— Via drill diameter (mm)

D— Pad diameter (mm)

D_a— Antipad (plane clearance) diameter (mm)

εᵣ— Dielectric constant

h— Via height (= board thickness) (mm)

How It Works

A plated through-hole via is, electrically, a short section of coaxial line. The plated barrel is the inner conductor; the clearance cut into every plane it passes through — the antipad — is the outer conductor. That identification is what makes the geometry tractable, and it also tells you which dimension controls which result.

Impedance follows the coaxial form directly: $Z = \frac{60}{\sqrt{\varepsilon_r}} \ln\frac{D_a}{d}$ , where $D_a$ is the antipad diameter and $d$ the drill. The pad does not appear. A 0.3 mm drill in a 1.0 mm antipad on FR-4 gives 35.2 Ω — well below a 50 Ω line, which is why an unmanaged via reads as a capacitive discontinuity.

Capacitance is the pad working against the antipad edge. IPC-2141A gives $C = \frac{0.0554\,\varepsilon_r\,T\,D}{D_a - D}$ pF with dimensions in millimetres, where $D$ is the pad diameter. Both plates appear and the gap between them is the denominator, so the plane clearance is the dominant lever: widening the antipad from 0.8 mm to 1.4 mm on a 0.6 mm pad cuts capacitance by a factor of three. The drill is not a plate and does not enter this expression at all.

Inductance comes from the barrel as a short round conductor over its return path, $L = 0.2h\left(\ln\frac{4h}{d} + 0.5\right)$ nH with $h$ and $d$ in millimetres. It grows with length and only logarithmically with diameter, so shortening a via helps far more than fattening it — which is the argument for back-drilling.

Current capacity works on the plated annulus. Copper deposits on the wall of the drilled hole, so it occupies the ring from radius $d/2 - t$ out to $d/2$ , giving $A = \pi t (d - t)$ . This is a much smaller cross-section than the hole suggests: a 0.3 mm via with 25 µm plating carries only 0.0216 mm² of copper, less than a third of what a solid plug of the same diameter would have.

Note that $Z$ here is the characteristic impedance of the via as a transmission-line section. It is not the same question as how much the via degrades a passing edge — for that, what matters is the excess reactance over what a matched section would have contributed, which the via step response calculator handles.

Worked Example

Given: 0.3 mm drill, 0.6 mm pad, 1.0 mm antipad, 1.6 mm FR-4 board (

\varepsilon_r = 4.2

), 25 µm barrel plating Step 1: Coaxial impedance

\sqrt{\varepsilon_r} = \sqrt{4.2} = 2.0493902

, so

\frac{60}{\sqrt{\varepsilon_r}} = 29.277002

\frac{D_a}{d} = \frac{1.0}{0.3} = 3.3333333

, and

\ln(3.3333333) = 1.2039728

Z = 29.277002 \times 1.2039728 = 35.2487

The pad diameter plays no part — only the barrel and the plane clearance form the coaxial pair.

Step 2: Pad-to-antipad capacitance (IPC-2141A)

0.0554 \times 4.2 = 0.232680

\times 1.6 = 0.372288

\times 0.6 = 0.2233728

C = \frac{0.2233728}{1.0 - 0.6} = 0.558432

pF Step 3: Barrel inductance

\frac{4h}{d} = \frac{4 \times 1.6}{0.3} = 21.333333

, and

\ln(21.333333) = 3.0602708

L = 0.2 \times 1.6 \times (3.0602708 + 0.5) = 0.32 \times 3.5602708 = 1.1392867

nH Step 4: Aspect ratio

\frac{T}{d} = \frac{1.6}{0.3} = 5.33

— comfortably inside the 10:1 limit standard fabrication handles. Step 5: Current capacity

t = 25

µm

= 0.025

mm, so

A = \pi \times 0.025 \times (0.3 - 0.025) = 0.02159845

mm²

= 33.478

mil²

I = 0.048 \times 10^{0.44} \times 33.478^{0.725} = 0.048 \times 2.7542287 \times 12.748159 = 1.6853

A Step 6: What it means for a 50 Ω line

\sqrt{L/C} = 45.17

Ω, below 50 Ω, so the via is capacitive. The excess over a matched section is

C - L/Z_0^2 = 0.5584 - 0.4557 = 0.1027

pF — only about a fifth of the raw capacitance is actually a discontinuity. Result: 35.2 Ω, 0.558 pF, 1.139 nH, 5.33:1 aspect ratio, 1.69 A at a 10 °C rise.

Practical Tips

✓Use via-in-pad with cap plating for BGA breakout — eliminates trace stub and reduces parasitic inductance by 30% per IPC-7095 recommendations.
✓Add ground vias within lambda/20 (2mm at 10 GHz) of signal vias — provides low-inductance return path, reducing via inductance by 40-60% per Johnson/Graham.
✓For RF/microwave (>6 GHz): specify back-drilling to within 0.1mm of signal layer — removes stub resonance and improves insertion loss by 3-6 dB per via.

Common Mistakes

✗Confusing the pad with the antipad — the pad is the copper ring on the via, the antipad is the clearance cut in the planes. Impedance depends on the antipad and not at all on the pad; capacitance depends on both. Swapping them understates impedance and makes capacitance insensitive to the one dimension that actually controls it
✗Assuming the barrel is solid copper — plating lines the wall of the drilled hole, so the conducting cross-section is the annulus pi*t*(d-t). A 0.3 mm via with 25 micrometre plating has 0.0216 square millimetres of copper, under a third of a solid plug of the same diameter
✗Reading the via characteristic impedance as the amount of signal degradation — a via whose square root of L over C already equals the line impedance is electrically invisible. What degrades an edge is the excess reactance over a matched section, not the raw L and C
✗Shrinking the antipad to reclaim plane copper — capacitance rises as the reciprocal of the clearance, so closing a 1.0 mm antipad to 0.8 mm on a 0.6 mm pad doubles the via capacitance
✗Using the board thickness for the barrel length on a back-drilled via — after back-drilling the signal only traverses the remaining length, and the full thickness overstates both inductance and capacitance

Frequently Asked Questions

How does via diameter affect impedance?

Impedance follows ln(antipad/drill), so a larger antipad or a smaller drill raises it. With a 0.25 mm drill on FR-4, a 0.5 mm antipad gives 20.3 ohm and a 0.7 mm antipad gives 30.1 ohm. Note how low those are: reaching 50 ohm needs an antipad-to-drill ratio of about 5.5, or a 1.38 mm antipad on that drill. Ordinary vias sit well under the line impedance, which is why they read as capacitive.

Why are via impedance calculations important?

Via discontinuities cause signal reflections: per IEEE 802.3 Ethernet specs, maximum via reflection coefficient is 5% for 10GBASE-T. A 60 ohm via on 50 ohm trace causes 9% reflection — failing spec. At 25 Gbps (100GBASE-CR4), via capacitance >0.3 pF causes 2 dB insertion loss, requiring HDI micro-vias.

Can via impedance be reduced?

To raise it, open the antipad or shrink the drill; to lower it, do the opposite. The practical limits are that a large antipad eats plane copper and can starve the return path, while a small antipad risks drill breakout into the clearance. Most designs settle for a via well below the line impedance and manage the resulting excess capacitance instead — by removing non-functional pads and back-drilling — rather than trying to hit 50 ohm with geometry alone.

How do different PCB materials affect via performance?

Impedance scales as one over the square root of the dielectric constant, so for identical geometry Rogers RO4350B (3.48) gives about 10 percent higher impedance than FR-4 (4.2), and PTFE (2.2) about 38 percent higher. Capacitance scales directly with the dielectric constant, so low-Er laminates cut via capacitance in the same proportion — useful at high speed for both reasons at once.

Are these formulas applicable to all frequencies?

The quasi-static formulas are accurate to +/-10% up to frequencies where via length < lambda/10. For 1.6mm board on FR4, this is approximately 4 GHz. Above 4 GHz, use full-wave EM simulation (HFSS, CST) for accurate S-parameters. Stub resonance effects become dominant above 3 GHz regardless of formula accuracy.

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