When a Trace Becomes a Transmission Line

The question that actually matters

Every trace is a transmission line. That's physics. The useful question isn't whether it is one — it's whether it behaves like one at the frequencies your signal carries.

A trace behaves like a transmission line when it's long enough for the signal to see a different impedance at the far end before the launch is finished. At that point reflections happen, and if you haven't terminated the line, those reflections ring.

Below the critical length, the trace is electrically short. The far end charges before the edge finishes transitioning, the whole thing looks like a lumped capacitor, and controlled impedance buys you nothing.

Two numbers

The propagation delay of a trace in FR4 is roughly 6.4 ns/m (about 170 ps/inch for inner layers, 140 ps/inch for outer). Multiply by length and you get the one-way flight time $T_D$.

The rise time $T_R$ is whatever the driver produces — not the clock period, not the data rate, the edge.

The ratio $T_R / T_D$ decides everything:

• $T_R / T_D > 5$ — trace is electrically short. No termination needed. The 20% rule: reflected energy is under 20% of the incident edge, which for most digital logic is below the noise margin.
• $T_R / T_D < 3$ — trace is electrically long. Terminate it. Without termination, the first reflection arrives before the edge settles, and it adds to (or subtracts from) the signal. Two reflections later you're ringing.
• Between 3 and 5 — depends on your noise budget and how much margin you have.

These thresholds come from Bogatin's analysis of the step response of a lossless line: at $k = 5$ the reflected step is 20% of the incident (the "20% rule"), and at $k = 3$ the round-trip reflection arrives during the transition, making it impossible to separate from the signal.

An example that surprises people

Take a 100 MHz clock. Period is 10 ns. "Slow," right?

But the driver is modern CMOS with a 300 ps rise time. The one-way delay of a 5 cm (2 inch) trace in FR4 is about 340 ps.

$T_R / T_D = 300 / 340 = 0.88$

That's deep into transmission-line territory. A 2-inch trace at 100 MHz needs controlled impedance and termination — not because 100 MHz is fast, but because 300 ps edges are fast.

Now take the same 100 MHz clock from a part with a 3 ns edge. Same trace:

$T_R / T_D = 3000 / 340 = 8.8$

Electrically short. Route it however you like.

The clock frequency told you nothing. The edge rate told you everything.

The judgment call

The 20% threshold at $k = 5$ is conservative for most logic. LVCMOS with 400 mV of noise margin can absorb a 20% reflection on a 3.3 V swing without flinching. LVDS with 100 mV of differential noise budget cannot.

So there's a judgment embedded in the number:

• High noise margin (GPIO, LED, reset): $k = 5$ or even $k = 3$ is fine. Don't terminate, don't control impedance, save the effort.
• Tight noise margin (DDR strobe, SerDes, LVDS): $k = 6$ or higher. Terminate everything.
• Somewhere in between: Use $k = 5$ as the default and tighten where the datasheet tells you to.

The point is that "critical length" isn't a physical constant. It's a design threshold that encodes your tolerance for reflections.

Propagation velocity isn't one number

I said 6.4 ns/m but that's an inner-layer average in FR4 at $\varepsilon_r \approx 4.2$. The actual velocity depends on the effective permittivity, which depends on the geometry:

• Stripline: $v = c / \sqrt{\varepsilon_r}$. Field is entirely in dielectric, so you use the bulk value.
  • Microstrip: $v = c / \sqrt{\varepsilon_{eff}}$. Part of the field is in air, so $\varepsilon_{eff} < \varepsilon_r$ and the trace is faster.
    • Coplanar waveguide: Somewhere between, depending on the filling factor.

    On Rogers 4350B ($\varepsilon_r = 3.66$) an inner-layer trace is about 10% faster than FR4. That means your critical length is 10% longer — the same trace that needed termination on FR4 might be fine on Rogers.

    For length matching between layers, this velocity difference is what you're compensating for. Two traces matched in millimetres but routed on different layers can be mismatched in picoseconds.

    Common mistakes

    Using the clock period instead of the rise time. The period tells you the repetition rate. The rise time tells you the bandwidth. A 25 MHz clock with 500 ps edges has a knee frequency of 1 GHz and needs transmission-line treatment on anything longer than about 1.5 cm. Using the datasheet typical rise time. Datasheets quote typical. Fast-corner silicon at low temperature with a light load can be 2-3x faster. Design to the fast corner. Ignoring the return path. A trace with a slot in its reference plane has a longer effective path — the return current detours around the slot. The physical length says "short" but the electrical length says "long," and the electrical length is what matters. Confusing delay with period. A trace becomes critical when $T_D$ approaches $T_R$, not when $T_D$ approaches the clock period. A trace that's one wavelength long at the fundamental is already 6-10x past the critical length for a typical edge.

    What to actually do

    1. Find the rise time. Datasheet fast corner, not typical.
    2. Measure or calculate the trace delay. Inner layer FR4 at 170 ps/inch is close enough for a first pass.
    3. Compute the ratio. If it's above 5, you're done. If it's below 3, terminate.
    4. In the grey zone, check your noise budget.

    The critical trace length calculator does this for you and gives both the conservative ($k = 5$) and permissive ($k = 3$) thresholds, plus the one-way delay and the knee frequency for your geometry.