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Dual Stripline Impedance Calculator

Calculate impedance for both signal layers of a dual stripline (two routing layers sharing one plane pair), plus the broadside crosstalk penalty when traces overlap.

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Formula

Z0n=2ZaZbZa+Zb,kb=Zeven−ZoddZeven+ZoddZ_{0n} = \frac{2 Z_a Z_b}{Z_a + Z_b},\qquad k_b = \frac{Z_{even} - Z_{odd}}{Z_{even} + Z_{odd}}

Reference: IPC-2141A; E. Bogatin, "Signal and Power Integrity — Simplified", 3rd ed., ch. 11

b— Plane-to-plane spacing (mm)
h₁— Layer 1 to upper plane (mm)
h₂— Layer 2 to lower plane (mm)
s— Separation between the two signal layers (mm)
k_b— Broadside backward-crosstalk coefficient

How It Works

Dual stripline puts two routing layers between one pair of reference planes. It is a cost play: you get two signal layers for the price of one plane pair, which on a dense board can save two copper layers and a lamination cycle. The price you pay is coupling between the two signal layers, and it has to be managed by routing discipline rather than by geometry.

Each signal layer on its own is simply an offset stripline. Layer 1 sits h1h_1 from the upper plane and s+t+h2s + t + h_2 from the lower one; layer 2 is the mirror. Both are solved with Cohn's parallel-half construction:

Z0=2ZaZbZa+ZbZ_{0} = \frac{2 Z_a Z_b}{Z_a + Z_b}

The other signal layer is deliberately not treated as a reference. It is a floating conductor, not a plane, and it carries its own signal. That assumption is exactly why the two layers must route orthogonally — the moment two traces run parallel over each other, the model stops applying and you have a broadside-coupled pair instead.

Why overlap is so damaging

When two traces on adjacent signal layers do run over each other, they face each other across a thin dielectric with no plane in between. That is the tightest coupling geometry available on a PCB. Decomposing into modes: odd mode places an electric wall midway between the traces, even mode places a magnetic wall there and leaves each trace referenced only to its own plane. The backward-crosstalk coefficient follows from the split:

kb=Zeven−ZoddZeven+Zoddk_b = \frac{Z_{even} - Z_{odd}}{Z_{even} + Z_{odd}}

For a typical dual-stripline geometry this lands around 20%, and climbs past 50% when the two signal layers sit closer to each other than to their planes — several times worse than the edge coupling between neighbouring traces on the same layer. That is not a number you design around; it is a number you avoid by routing one layer north-south and the other east-west.

Impedance asymmetry

Unless the stack-up is symmetric, the two layers will not have the same impedance. Whichever layer sits closer to its plane is the lower-impedance one. If both need to hit the same target, use different trace widths per layer and tell the fabricator both values.

Worked Example

Problem: A 6-layer board has ground on L2 and L5, with signal layers on L3 and L4. Plane-to-plane spacing is 0.8 mm, L3 sits 0.2 mm below L2, the two signal layers are 0.33 mm apart, copper is 1 oz, FR4 er = 4.2. Find both impedances and the worst-case coupling.

Step 1 - Derive the lower gap: h2 = b - h1 - s - 2t = 0.8 - 0.2 - 0.33 - 0.07 = 0.2 mm The stack-up is symmetric, so both layers should match.

Step 2 - Layer 3 impedance, 0.13 mm trace. Near gap 0.2 mm, far reference at s + t + h2 = 0.565 mm. Mirroring each half about its own plane gives two equivalent symmetric striplines: Z_a (b = 0.435 mm) = 50.04 ohm Z_b (b = 1.165 mm) = 78.55 ohm Combining the halves and restoring the fringing that plain superposition omits: Z0 = 60.51 ohm

Step 3 - Layer 4 is the mirror image, so also 60.51 ohm. Confirmed symmetric.

Step 4 - Worst-case broadside coupling if the layers overlap. Odd mode places an electric wall midway between the traces at s/2 = 0.165 mm; even mode replaces it with a magnetic wall, so each trace is referenced to its own plane but still sees some field past the wall. Z_odd = 47.45 ohm, Z_even = 73.52 ohm k_b = (73.52 - 47.45)/(73.52 + 47.45) = 21.6%

Step 5 - Interpretation. Over a fifth of the aggressor voltage appears on the victim if the two traces run parallel over each other — several times worse than the edge coupling between neighbours on the same layer at normal spacing. Route L3 horizontally and L4 vertically; overlap then reduces to isolated crossings, where the coupled length is a fraction of a millimetre and the crosstalk is negligible.

Practical Tips

  • ✓Route the two layers orthogonally without exception. Enforce it with a design rule, not with reviewer discipline.
  • ✓Give each layer its own trace width if the stack-up is asymmetric, and put both widths on the fabrication drawing.
  • ✓Keep the two signal layers as far apart as the stack-up allows and each layer as close as possible to its own plane — that is the geometry that minimises coupling.
  • ✓If you must run two nets parallel across layers, make sure they are unrelated and slow. Never do it with a clock or a strobe.
  • ✓Where the budget allows a plane between the two signal layers, take it. Dual stripline is a cost compromise, not a performance choice.
  • ✓Check the reported coupling coefficient before committing to the stack-up. Above about 10%, the orthogonality rule stops being advice and becomes a hard requirement.

Common Mistakes

  • ✗Routing both signal layers in the same direction. Overlapping broadside traces typically couple at around 20%, and far more when the layers are close together — no amount of spacing within a layer fixes it.
  • ✗Assuming both layers have the same impedance. They only match if the stack-up is symmetric; otherwise the layer nearer its plane is lower.
  • ✗Treating the other signal layer as a reference plane in the impedance model. It is a floating conductor carrying its own signal, and modelling it as ground gives an optimistically low impedance.
  • ✗Putting a differential pair on one dual-stripline layer and a fast single-ended clock on the other, directly above it. The clock couples into the pair as common mode, which the receiver cannot reject.
  • ✗Forgetting to add the two copper thicknesses when deriving the second layer offset from the plane spacing — a 0.07 mm error on a 0.2 mm gap is a 35% error in the wrong place.

Frequently Asked Questions

Two signal routing layers placed between the same pair of reference planes, with no plane in between them. It saves copper layers and cost compared with giving each signal layer its own plane pair.
In practice, yes. Traces facing each other across a thin dielectric with no intervening plane are the most tightly coupled structure on a PCB — commonly around 20% backward crosstalk, and far more on tight stack-ups. Routing one layer horizontally and the other vertically reduces the coupled length at each crossing to almost nothing.
Because they sit at different distances from their nearer plane. The layer closer to its plane has the lower impedance. Fix it with different trace widths per layer rather than by trying to force a symmetric stack-up.
Yes, provided the orthogonality rule holds and nothing fast runs directly over the pair on the adjacent layer. Broadside coupling from an aggressor above appears as common mode on the pair, which the receiver's rejection cannot remove.
On dense, cost-sensitive designs, yes — two layers saved is real money at volume. On high-speed designs with tight crosstalk budgets, put a plane between the signal layers instead and accept the extra cost.

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