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Planar Spiral Inductor Calculator

Calculate PCB planar spiral inductance using Mohan current-sheet and modified Wheeler methods for square, hexagonal, octagonal, and circular geometries.

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Formula

L=μ0n2davgc12[ln⁡c2ρ+c3ρ+c4ρ2]L = \frac{\mu_0 n^2 d_{avg} c_1}{2} \left[ \ln\frac{c_2}{\rho} + c_3\rho + c_4\rho^2 \right]

Reference: Mohan et al., "Simple Accurate Expressions for Planar Spiral Inductances", IEEE JSSC, vol. 34, no. 10, Oct 1999

N— Number of turns
d_avg— Average diameter (d_out + d_in) / 2 (mm)
ρ— Fill ratio (d_out − d_in) / (d_out + d_in)
c₁–c₄— Shape-dependent Mohan coefficients

How It Works

A planar spiral inductor is a flat coil patterned directly on a PCB layer. Current flowing through the spiral generates a magnetic field perpendicular to the board, and the mutual coupling between turns produces useful inductance. Unlike discrete inductors, planar spirals have no core — their inductance comes entirely from the geometry.

The Mohan current-sheet approximation (IEEE JSSC 1999) models the spiral as a set of concentric current sheets and provides closed-form expressions accurate within 2–3% for fill ratios below 0.8. The key parameter is the fill ratio ρ = (d_out − d_in) / (d_out + d_in), which measures how tightly the turns are packed. Low fill ratio (< 0.3) means a mostly hollow coil — high Q but low inductance per area. High fill ratio (> 0.6) packs more turns but increases DC resistance and proximity losses, degrading Q.

Four geometries are commonly used: square (easiest layout, lowest Q), hexagonal, octagonal, and circular (highest Q, hardest to route). The Mohan coefficients c₁–c₄ capture shape-dependent field distribution. The modified Wheeler formula provides an independent estimate; averaging both gives improved accuracy.

Worked Example

Given: Outer diameter = 10 mm, inner diameter = 4 mm, turns = 5, square geometry Step 1: Fill ratio and average diameter ρ=dout−dindout+din=10−410+4=0.4286\rho = \frac{d_{out} - d_{in}}{d_{out} + d_{in}} = \frac{10 - 4}{10 + 4} = 0.4286 davg=10+42=7d_{avg} = \frac{10 + 4}{2} = 7 mm Step 2: Mohan current-sheet (square: c₁=1.27, c₂=2.07, c₃=0.18, c₄=0.13) μ0=4π×10−4\mu_0 = 4\pi \times 10^{-4} nH/mm L=μ0N2davgc12[ln⁡c2ρ+c3ρ+c4ρ2]L = \frac{\mu_0 N^2 d_{avg} c_1}{2} \left[ \ln\frac{c_2}{\rho} + c_3\rho + c_4\rho^2 \right] =1.2566×10−3×25×7×1.272×[ln⁡2.070.4286+0.18×0.4286+0.13×0.1837]= \frac{1.2566 \times 10^{-3} \times 25 \times 7 \times 1.27}{2} \times \left[ \ln\frac{2.07}{0.4286} + 0.18 \times 0.4286 + 0.13 \times 0.1837 \right] =0.1399×[1.574+0.0771+0.0239]= 0.1399 \times [1.574 + 0.0771 + 0.0239] =0.1399×1.675=234= 0.1399 \times 1.675 = 234 nH Step 3: DC resistance (1 oz Cu, 0.3 mm trace)

Total length =N×π×davg=5×π×7=110= N \times \pi \times d_{avg} = 5 \times \pi \times 7 = 110 mm

RDC=1.724×10−5×1100.3×0.035=0.181R_{DC} = \frac{1.724 \times 10^{-5} \times 110}{0.3 \times 0.035} = 0.181 Ω Step 4: Q at 100 MHz XL=2π×100×106×234×10−9=147X_L = 2\pi \times 100 \times 10^6 \times 234 \times 10^{-9} = 147 Ω Q=XL/RDC=147/0.181≈812Q = X_L / R_{DC} = 147 / 0.181 ≈ 812

(Note: this overestimates Q because skin effect and substrate losses are not included. Practical Q at 100 MHz is typically 20–50 for PCB spirals.)

Practical Tips

  • ✓Target fill ratio 0.3–0.5 for maximum Q. Increase only if board area is severely constrained
  • ✓Use circular geometry when Q matters; square when you need simple DRC and easy routing to the centre tap
  • ✓Place the spiral at least 3× trace width away from the ground plane (use thicker dielectric or internal layers)
  • ✓For differential inductors, interleave two spirals on the same layer to maximise coupling coefficient
  • ✓Verify with a VNA up to 2× your operating frequency — the SRF estimate from simple models can be off by 2×

Common Mistakes

  • ✗Using the formula outside its valid range — Mohan accuracy degrades above ρ = 0.8; use EM simulation for tightly wound spirals
  • ✗Ignoring skin effect in Q estimation — DC resistance underestimates losses at RF by 5–10×; skin depth at 1 GHz in copper is only 2.1 µm
  • ✗Making the inner opening too small — a solid centre adds resistance without proportional inductance gain; keep fill ratio below 0.6 for best Q
  • ✗Forgetting that the ground plane reduces inductance — a ground plane closer than 3× the trace width partially shorts the magnetic field, reducing L by 10–30%

Frequently Asked Questions

Typically 1–500 nH on standard 2-layer boards. Multi-layer stacking (series connection through vias) can reach 1–5 µH. Above 500 nH on a single layer, the required area and DC resistance usually make a discrete inductor more practical.
Inductance scales approximately as N² (Mohan formula). Doubling turns from 3 to 6 gives roughly 4× the inductance — but also 2× the resistance and half the SRF.
PCB traces are thin (35 µm for 1 oz copper), so skin-effect resistance is high at RF. Substrate losses (eddy currents in ground plane, dielectric loss in FR4) further degrade Q. Typical PCB inductor Q is 20–50 at 1 GHz, versus 50–150 for SMD chip inductors.
Yes — series-connected spirals on adjacent layers roughly double the inductance (mutual coupling adds). Parallel-connected spirals halve the resistance for the same inductance. Via transitions add parasitic capacitance, lowering SRF.
The SRF is where parasitic capacitance (inter-turn, trace-to-ground) resonates with the inductance, making the spiral behave as a capacitor above that frequency. You must operate well below SRF — typically at f < SRF/3 — for the component to function as an inductor.

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