PDN Impedance Analysis: Cavity Resonances, Decoupling Optimization, and the Flat Impedance Profile

The Invisible Problem on Every High-Speed PCB

Your 1.0V core rail looks clean on an oscilloscope. The LDO regulation spec says 50mV ripple, and you measure 30mV. Everything looks fine — until the FPGA fails to configure, the DDR controller throws occasional ECC errors, or the RF front-end spurs appear at unexpected offsets.

Power delivery network (PDN) impedance is the culprit in more board failures than most engineers realize. The voltage rail isn't just ripple at the switching frequency: it's a transmission medium with frequency-dependent impedance, resonances, and anti-resonances that the processor's current demand excites across a bandwidth of DC to several hundred megahertz. A flat, low PDN impedance profile across that entire bandwidth is the engineering goal — and it requires modeling cavity resonances, not just placing bulk capacitors.

This walkthrough uses the PDN Impedance Analyzer to design the power delivery network for a mid-range FPGA core rail.

Target Impedance: Working Backwards from dV Budget

The first calculation is the target impedance:

For a 1.0V core rail with ±5% ripple budget and a worst-case transient of 2A (LUT switching), the target is:

This 25 mΩ target must be met from DC to the highest frequency at which significant current transients occur — for this FPGA, approximately 300 MHz. Enter the VRM parameters: 100 μH inductance (a typical point-of-load converter), 5 mΩ DCR, and 10 MHz bandwidth (the closed-loop bandwidth of the POL regulator). These parameters determine where the VRM stops providing effective regulation and where the capacitors must take over.

Plane-Pair Cavity Resonances

A 100mm × 80mm four-layer board with 4 mil FR-4 between power and ground planes has a characteristic impedance and resonant modes that appear like LC circuits in the PDN impedance profile. The lowest cavity resonance frequency is:

For (m=1, n=0) on a 100mm board with FR-4 (ε_r = 4.3):

Enter the board dimensions and dielectric constant into the tool. The impedance plot immediately shows the anti-resonance peaks: sharp spikes at 723 MHz, 1.03 GHz, and 1.26 GHz where the cavity looks like a high-impedance LC resonator. Between these peaks, the cavity impedance drops — the planes are actually helping. But without decoupling capacitors, the impedance exceeds the 25 mΩ target across most of the 10 MHz–300 MHz band.

Capacitor Selection: Why the Database Matters

The tool includes a database of common 0402, 0201, and 0105 MLCC capacitors with measured ESR, ESL, and capacitance values. This matters because a capacitor's self-resonant frequency (SRF) determines where it provides its minimum impedance:

A 100 nF 0402 capacitor with 400 pH ESL resonates at 25 MHz. Below that frequency it behaves as a capacitor; above it, as an inductor. A 1 nF 0201 with 150 pH ESL resonates at 130 MHz. Effective PDN design staggers multiple capacitor values to maintain the cascade of resonances below the target impedance — a technique called capacitor value interleaving.

Running the Genetic Algorithm Optimizer

Set the optimization target: achieve Z < 25 mΩ from DC to 300 MHz, using the capacitor library with a maximum of 20 capacitors total. Enable the genetic algorithm with 300 generations.

The GA minimizes a fitness function that penalizes impedance violations above the target and total capacitor count. After convergence (typically 200–250 generations for this board size), the optimizer selects:

• 4× 10 μF 0402 (bulk, covers 100 kHz–5 MHz)
• 6× 100 nF 0402 (mid-frequency, covers 5–50 MHz)
• 6× 10 nF 0201 (high-frequency, covers 50–200 MHz)
• 4× 1 nF 0201 (covers 200–500 MHz)

The resulting impedance profile is flat at 8–15 mΩ from 100 kHz to 280 MHz — well under the 25 mΩ target. Above 300 MHz, the cavity resonances dominate and impedance rises, but no significant current transients exist at those frequencies for this FPGA.

The Convergence History Tells You If You Need More Capacitors

Watch the convergence history chart as the GA runs. A plateau after generation 100 with fitness still above the constraint means you've hit a local minimum — try adding one more high-frequency capacitor type to the allowed library. A smooth monotonic decrease to zero fitness means the target is achievable with fewer capacitors than the maximum.

For the 20-capacitor budget in this example, convergence reaches zero fitness by generation 180. Reducing the budget to 16 capacitors still achieves zero fitness (the 4× 1 nF caps are unnecessary below 300 MHz), saving board area and BOM cost.

The Anti-Resonance Problem

One result the tool highlights immediately: the anti-resonance between the 10 μF and 100 nF capacitors at approximately 8 MHz. Where the 10 μF cap transitions from capacitive to inductive behavior and the 100 nF cap transitions from capacitive to capacitive, the two capacitors form a parallel LC circuit with a high impedance peak. The tool shows this as a spike at 8 MHz.

The fix is to add a damping resistor in series with one of the capacitor values, or to add an intermediate 1 μF value to bridge the gap. The latter is what the GA discovers when run without a budget constraint: it independently places 1 μF capacitors exactly where the anti-resonance would appear.

This is the central insight of PDN design: you're not just bypassing noise, you're designing an impedance spectrum. The GA discovers what decades of experience-driven heuristics have codified — and it does it in under 30 seconds.

PDN Impedance Analyzer