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PCB Power Plane Impedance Calculator

Calculate PCB power plane impedance, capacitance, inductance, and resonant frequency for PDN design. Optimize your power delivery network. Free, instant results.

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Formula

C=εrε0Ad,fres=12πLCC = \frac{\varepsilon_r \varepsilon_0 A}{d},\quad f_{res} = \frac{1}{2\pi\sqrt{LC}}

Reference: IPC-2141A / Larry Smith PDN analysis techniques

εr— Dielectric constant
A— Plane area (m²)
d— Dielectric thickness (m)
f_res— Self-resonant frequency (Hz)

How It Works

The Power Plane Impedance Calculator computes characteristic impedance and self-resonant frequency for PCB power distribution networks — essential for achieving target impedance below 100 mohm across DC to 500 MHz in high-speed digital designs. PDN engineers use this to ensure supply noise stays below IC specifications (typically 5% of Vdd) during high-frequency transient current demands.

Per Larry Smith's 'High-Speed Digital System Design' and Steve Sandler's 'Power Integrity,' power plane capacitance C = epsilon_0 x epsilon_r x A / d, where A is plane area and d is dielectric thickness. A 100 cm2 plane with FR4 (Er=4.3) and 0.1mm dielectric has C = 3.8 nF — providing low impedance at high frequencies where discrete capacitors become inductive.

Plane inductance L = mu_0 x d / A x spreading_factor, creating self-resonant frequency f_SRF = 1 / (2 x pi x sqrt(L x C)). Typical 4-layer boards resonate at 100-500 MHz. Below SRF, impedance is capacitive (decreasing with frequency); above SRF, impedance is inductive (increasing with frequency). Per Smith, target PDN impedance requires controlling this resonance.

Per IPC-2152 PDN guidelines, target impedance Z_target = deltaV / deltaI. For a 1V FPGA allowing 50mV noise with 2A transient: Z_target = 0.05/2 = 25 mohm from DC to 500 MHz. Achieving this requires distributed plane capacitance plus strategic decoupling capacitor placement to fill impedance gaps at different frequency bands.

Worked Example

Problem: Calculate power plane capacitance, inductance, and SRF for 4-layer board with 80x60mm power-ground plane pair (4800 mm2), 0.1mm FR4 dielectric (Er=4.3).

Solution per Smith:

  1. Plane capacitance: C = 8.854e-12 x 4.3 x 4800e-6 / 0.1e-3 = 1.83 nF
  2. Plane inductance: L = 4 x pi x 1e-7 x 0.1e-3 / (4800e-6) = 26.2 pH
  3. SRF: f_SRF = 1 / (2 x pi x sqrt(26.2e-12 x 1.83e-9)) = 726 MHz
  4. Characteristic impedance: Z0 = sqrt(L/C) = sqrt(26.2e-12/1.83e-9) = 3.8 mohm
  5. Verify target impedance at 500 MHz: X_C = 1/(2 x pi x 500e6 x 1.83e-9) = 174 mohm
Analysis: Plane alone provides 174 mohm at 500 MHz — above typical 25 mohm target. Requires decoupling capacitors (100 nF, 10 nF) to achieve target. Below SRF (726 MHz), plane capacitance helps; above SRF, plane inductance dominates.

Practical Tips

  • ✓Use thin dielectric (<0.1mm) between power-ground planes — per Smith, halving dielectric doubles capacitance and halves inductance, reducing impedance by 4x. HDI boards with 50um cores achieve <10 mohm plane impedance.
  • ✓Minimize plane splits — per Sandler, splits increase inductance and disrupt return currents, creating impedance spikes at split boundaries. Use continuous planes where possible; if splits needed, add via stitching across.
  • ✓Place decoupling capacitors at plane anti-resonance frequencies — per Smith, identify impedance peaks from simulation or measurement, then add capacitors with SRF at those frequencies to flatten response.

Common Mistakes

  • ✗Ignoring plane inductance in PDN design — per Smith, plane inductance creates anti-resonances with decoupling capacitors at specific frequencies, potentially increasing impedance 10-100x at those frequencies. Use PDN simulation to identify and damp resonances.
  • ✗Using uniform plane impedance assumption — per Sandler, impedance varies across plane area; edges have 2-3x higher impedance than center due to spreading resistance. Place high-transient ICs near plane center, not at edges.
  • ✗Relying on plane capacitance alone — 1.8 nF plane capacitance provides only 170 mohm at 500 MHz. Per IPC-2152, typical designs need 10x lower impedance, requiring parallel decoupling capacitors.

Frequently Asked Questions

Four parameters per Smith: (1) Plane area — larger area increases capacitance, decreases inductance; (2) Dielectric thickness — thinner is better for both C and L; (3) Dielectric constant Er — higher Er increases capacitance; (4) Copper losses — become significant above 1 GHz. A 100 cm2 plane with 0.1mm FR4 has approximately 2 nF capacitance; with 0.05mm dielectric, 4 nF.
Per Sandler: Z_target = allowable_noise / max_transient_current. For modern processors (1V core, 3% noise budget = 30mV, 5A transients): Z_target = 30mV/5A = 6 mohm from DC to 500 MHz. FPGAs typically require 10-25 mohm. Simple MCUs with slower edges (>5ns) can tolerate 50-100 mohm per JEDEC guidelines.
Plane resonance occurs at f_SRF where capacitive and inductive reactances equal. At resonance, impedance equals ESR of the plane (typically <10 mohm). However, anti-resonances between plane and decoupling capacitors can create impedance peaks 10-100x higher than target. Per Smith, these peaks cause supply noise at specific frequencies that may fail IC specs.
Per IPC-2152: (1) Add decoupling capacitors with SRF near 100 MHz (10-100 nF MLCCs); (2) Use multiple parallel capacitors to reduce effective ESL; (3) Place capacitors close to ICs (<3mm) to minimize trace inductance; (4) Use power-ground plane pairs with thin dielectric. A single 100 nF capacitor provides 16 mohm at 100 MHz; four in parallel provide 4 mohm.
Yes — per Sandler, rectangular planes have higher inductance at edges than square planes of equal area. L-shaped or irregular planes create impedance discontinuities at bends. Spreading resistance increases impedance for off-center loads by 2-3x. Use rectangular or square planes; place high-current ICs near geometric center for minimum impedance.

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