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Microvia Current Capacity Calculator

Calculate laser-drilled microvia current capacity from barrel cross-section using IPC-2221, with DC resistance, voltage drop, current density, self-heating, and IPC-2226 aspect-ratio checks.

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Formula

A=π t (D−t),I=k ΔT0.44Amil20.725,k={0.024internal0.048externalA = \pi\, t\,(D - t), \qquad I = k\,\Delta T^{0.44} A_{\text{mil}^2}^{0.725}, \qquad k = \begin{cases} 0.024 & \text{internal} \\ 0.048 & \text{external} \end{cases}

Reference: IPC-2221B (conductor current capacity); IPC-2226 (HDI design, microvia definition and aspect ratio); IPC-6012 (plating thickness classes); IPC-TM-650 2.6.27 (microvia thermal shock)

A— Plated barrel cross-section (thin-wall annulus) (mm² / mil²)
D— Laser-drilled microvia diameter (mm)
t— Barrel plating thickness (µm)
L— Microvia depth (dielectric thickness) (mm)
ΔT— Allowed temperature rise above ambient (°C)
k— IPC-2221 conductor-class constant
J— Current density in the barrel (A/mm²)

How It Works

A microvia is a laser-drilled blind via connecting two adjacent layers. IPC-2226 defines it by geometry rather than by process: 0.15 mm diameter or less, with a depth-to-diameter aspect ratio of 1:1 or better. Its plated barrel is a thin-wall annulus, since copper deposits on the wall of the drilled hole and occupies the region from radius D/2−tD/2 - t out to D/2D/2. The conducting area is therefore A=πt(D−t)A = \pi t (D - t), which for a 100 µm microvia with 18 µm plating is only about 0.00464 mm² — roughly a fifth of what a 0.3 mm through-hole via offers. That small number is why current capacity is asked about at all.

IPC-2221 gives conductor current capacity as I=kΔT0.44A0.725I = k \Delta T^{0.44} A^{0.725} with AA in square mils. The exponents come from a fit to measured trace data, and the sub-linear area dependence reflects that a wider conductor also has more of itself far from any cooling surface. The constant kk encodes how easily heat escapes: IPC specifies 0.024 for internal conductors buried in laminate and 0.048 for external ones on an outer surface, a factor-of-two derating for being buried.

Which value applies to a microvia is genuinely ambiguous, and this calculator reports both rather than pretending otherwise. A microvia is buried, arguing for 0.024. But it is also only 50–100 µm long and bonded at both ends to copper pads that conduct heat far better than laminate does, arguing for 0.048. Measured microvia capacity generally falls between the two bounds, and typical HDI design rules budgeting 0.5–1 A per microvia sit near the upper one.

The self-heating outputs make the more important point. DC resistance is R=ρ(T)L/AR = \rho(T) L / A, and because LL is so small a microvia comes out well under a milliohm — several times lower than a through-hole via despite having far less copper, since the length term dominates. Modelling the barrel as a conduction path of thermal resistance θ=L/(kCuA)\theta = L/(k_{Cu} A) then gives a steady-state rise of thousandths of a degree at realistic currents. The barrel is not what fails. What fails is the target-pad interface: under thermal cycling the z-axis expansion of the dielectric pulls the plated barrel away from the pad it lands on, and microvia reliability is qualified by thermal shock testing per IPC-TM-650 2.6.27, not by any current formula. Treat the IPC-2221 figure as a plating and electromigration guardrail rather than a prediction of measured temperature.

Worked Example

Given: 0.1 mm microvia, 18 µm barrel plating, 0.075 mm depth, 10 °C allowed rise, 0.25 A design current, single via, 25 °C ambient Step 1: Barrel cross-section A=πt(D−t)=π×18×10−6×(100−18)×10−6A = \pi t (D - t) = \pi \times 18 \times 10^{-6} \times (100 - 18) \times 10^{-6} =π×18×82×10−12=4.636990756698534×10−9= \pi \times 18 \times 82 \times 10^{-12} = 4.636990756698534 \times 10^{-9} m² =0.004636990756698534= 0.004636990756698534 mm²

Converted to the units IPC-2221 expects: 4.63699×10−96.4516×10−10=7.18736\frac{4.63699 \times 10^{-9}}{6.4516 \times 10^{-10}} = 7.18736 mil²

Step 2: IPC-2221 current capacity, both classes Iinternal=0.024×100.44×7.187360.725=0.024×2.754229×4.178702=0.2761999651813298I_{internal} = 0.024 \times 10^{0.44} \times 7.18736^{0.725} = 0.024 \times 2.754229 \times 4.178702 = 0.2761999651813298 A Iexternal=0.048×2.754229×4.178702=0.5523999303626596I_{external} = 0.048 \times 2.754229 \times 4.178702 = 0.5523999303626596 A

The honest answer for a microvia lies between 0.28 A and 0.55 A.

Step 3: DC resistance at 25 °C ρ=ρ20[1+α(T−20)]=1.724×10−8×[1+0.00393×5]=1.757877×10−8\rho = \rho_{20}[1 + \alpha(T - 20)] = 1.724 \times 10^{-8} \times [1 + 0.00393 \times 5] = 1.757877 \times 10^{-8} Ω·m R=ρLA=1.757877×10−8×75×10−64.636991×10−9=2.8432393×10−4 Ω=0.28432393316623417R = \frac{\rho L}{A} = \frac{1.757877 \times 10^{-8} \times 75 \times 10^{-6}}{4.636991 \times 10^{-9}} = 2.8432393 \times 10^{-4}\ \Omega = 0.28432393316623417 mΩ Step 4: Drop and dissipation at 0.25 A V=IR=0.25×2.8432393×10−4=0.07108098329155854V = IR = 0.25 \times 2.8432393 \times 10^{-4} = 0.07108098329155854 mV P=I2R=0.0625×2.8432393×10−4=0.017770245822889635P = I^2 R = 0.0625 \times 2.8432393 \times 10^{-4} = 0.017770245822889635 mW Step 5: Barrel self-heating θ=LkCuA=75×10−6385×4.636991×10−9=42.011\theta = \frac{L}{k_{Cu} A} = \frac{75 \times 10^{-6}}{385 \times 4.636991 \times 10^{-9}} = 42.011 °C/W ΔT=Pθ=1.7770×10−5×42.011=0.0007465480051396345\Delta T = P \theta = 1.7770 \times 10^{-5} \times 42.011 = 0.0007465480051396345 °C

Seven ten-thousandths of a degree. The IPC-2221 capacity limit and the actual barrel temperature rise are describing two entirely different things.

Step 6: Geometry and density checks J=IA=0.250.004636991=53.914J = \frac{I}{A} = \frac{0.25}{0.004636991} = 53.914 A/mm²

Aspect ratio =0.0750.1=0.75= \frac{0.075}{0.1} = 0.75 — at the value most fabricators prefer, and inside the 1:1 IPC-2226 limit.

Result: 0.28 A conservative capacity per via, 0.55 A optimistic, 0.284 mΩ resistance, and negligible self-heating. For a 2 A rail, use eight to ten microvias.

Practical Tips

  • ✓Budget roughly 0.5 A per 100 micrometre microvia in normal HDI practice, then check it against both bounds here. If your requirement sits above the external-class figure, add vias rather than arguing about the constant
  • ✓Use the array outputs rather than scaling by hand. Resistance divides by N and capacity multiplies by N, but current sharing between parallel microvias is never perfectly even, so keep 20 to 30 percent margin
  • ✓For power delivery, microvias are genuinely excellent — their short length gives lower resistance than a through-hole via despite the smaller cross-section. The limitation is mechanical reliability, not electrical performance
  • ✓Keep the aspect ratio at or below 0.75:1 if you can. It is the single geometry parameter that most affects yield and long-term reliability, and it costs nothing at design time
  • ✓Check current density as well as total current. Above roughly 100 A per square millimetre, electromigration and plating voids become a concern that no temperature-rise calculation will reveal

Common Mistakes

  • ✗Using the full drilled area pi-D-squared-over-4 instead of the thin-wall annulus — a standard microvia is a hollow plated barrel, not a solid copper plug, and the solid assumption overstates the area by roughly five times
  • ✗Treating the IPC-2221 capacity as a measured temperature prediction — it is an empirical trace rule applied to a barrel cross-section. The calculator shows both it and the actual barrel self-heating, and they disagree by orders of magnitude for a reason
  • ✗Ignoring the aspect ratio — beyond 1:1 the laser-drilled hole tapers too sharply for plating chemistry to reach the target pad uniformly, and the thin plating at the base becomes the failure point regardless of what the current formula says
  • ✗Stacking microvias to save routing area on a high-current path — stacked interfaces accumulate thermo-mechanical stress and are the most common HDI failure mode under thermal cycling. Stagger them where the layout allows
  • ✗Designing to nominal plating thickness — IPC-6012 Class 2 permits 18 micrometres minimum against a 20 micrometre average, and capacity scales as area to the 0.725 power, so worst-case plating is the number to design against

Frequently Asked Questions

With 18 micrometre plating and a 10 degree C rise, the conservative internal-conductor figure is about 0.28 A and the external-conductor bound about 0.55 A. Most HDI design rules budget 0.5 to 1 A per microvia, which sits at or slightly above the upper bound — reasonable given how well the pads sink heat, but worth verifying near the limit.
Because resistance is rho times length divided by area, and the length term wins. A microvia has roughly a fifth the copper area of a 0.3 mm through-hole via but is only about 5 percent as long, so it ends up several times lower in resistance. This is why microvias are excellent for power delivery in HDI stack-ups.
Because the barrel is genuinely not the thermal bottleneck. At 0.25 A the dissipation is under 0.02 mW and the conduction path to the pads is very short. The IPC-2221 capacity figure is an empirical trace rule applied to the barrel cross-section and is intentionally conservative — treat it as a plating and electromigration guardrail, not a prediction of measured temperature.
IPC-2226 sets 1:1 depth-to-diameter as the limit and most fabricators prefer 0.75:1 or lower. Beyond that the laser-drilled hole tapers too sharply for the plating chemistry to reach the target pad with uniform thickness, and the thin plating at the base becomes the reliability failure point.
Stagger them where you can. Stacked microvias give a shorter lower-resistance path and save routing area, but the stacked interfaces accumulate thermo-mechanical stress and are the most common HDI failure mode under thermal cycling. Staggered microvias with a solid pad between layers are substantially more robust.
Using the conservative 0.28 A per via at 10 degrees C rise, 2 A needs eight vias, and rounding up to ten gives margin for plating variation and uneven current sharing. A tight cluster under the pad is standard practice, and the array resistance and voltage drop outputs let you check the delivered rail accuracy at the same time.

Related Articles

PCB Design

How Much Current Can a Microvia Carry?

A 100 µm microvia has a fifth the copper of a through-hole via and a fraction of its resistance. The IPC-2221 current formula gives two different answers depending on a constant nobody can definitively pick — and neither is what actually fails.

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