PCB Trace Inductance Calculator
Calculate PCB trace parasitic inductance using the Ruehli formula. Get inductance per unit length and impedance at 100 MHz and 1 GHz. Free, instant results.
Formula
How It Works
The PCB Trace Inductance Calculator computes the partial self-inductance of a straight, rectangular PCB trace from its length, width and copper thickness — essential for power distribution network (PDN) design, decoupling capacitor placement, and high-frequency signal integrity. Partial inductance is the trace's own share of the inductance of whatever loop its current flows in; at 100 MHz, every nanohenry of it between a capacitor and an IC pin adds 0.63 Ω of reactance. The calculator models the trace on its own: it has no input for the height above a ground plane, so it gives the same result for a microstrip, a stripline or a trace with no plane at all.
It uses Ruehli's closed form for a rectangular conductor: , where l is the trace length, w the trace width and t the copper thickness. A 50 mm trace, 0.3 mm wide in 1 oz (35 µm) copper, comes to 62.0 nH, or 1.24 nH/mm. At 100 MHz that is 39.0 Ω of reactance, far above the trace's DC resistance of 82 mΩ.
Inductance dominates a trace's impedance above the crossover frequency , where R is its DC resistance. In 1 oz copper that is about 210 kHz for the 50 mm, 0.3 mm trace above, 50 kHz for the worked example's 30 mm, 2 mm power trace and 395 kHz for the calculator's default 10 mm, 0.2 mm trace. Above it, shortening a trace or adding parallel paths (copper pours) lowers impedance more than widening does: width enters only through the logarithm, while each parallel path divides the inductance, provided the paths are far enough apart that their mutual inductance is small.
Loop inductance is a different quantity, and the calculator does not report it. A trace's current returns through the reference plane beneath it, and what sets ground bounce and radiated emissions is the inductance of the whole loop: the closer the plane, the more of the trace's field the return current cancels. Per unit length, the loop inductance of a microstrip is , its impedance times its propagation delay per unit length, both of which the microstrip impedance calculator reports. For the 0.3 mm trace above, that is 0.62 nH/mm with the plane 1 mm below and 0.22 nH/mm at 0.1 mm, a 65% reduction, against 1.24 nH/mm of partial inductance. For a trace much wider than its height above the plane, is a quick estimate, as in the worked example; it reads somewhat high because it ignores the fringing field. This is why controlled impedance designs place signal layers next to ground planes.
Worked Example
Problem: Calculate the inductance of a 30mm power trace (2mm wide, 1oz copper) supplying a 1 GHz FPGA with a 3A transient current demand in 1ns.
Solution per Ruehli (the formula the calculator uses):
- Trace parameters: l = 30mm, w = 2mm, t = 35µm (1oz)
- Inductance: L = (μ0 × l / 2π) × [ln(2l/(w+t)) + 0.5 + (w+t)/(3l)]
- L = 2e-7 × 0.03 × [ln(0.06/0.002035) + 0.5 + 0.002035/0.09] = 6e-9 × [3.384 + 0.5 + 0.023] = 6e-9 × 3.907 = 23.4 nH
- Per unit length: 23.4 nH / 30mm = 0.78 nH/mm; reactance at 1 GHz = 2π × 1e9 × 23.4e-9 = 147Ω
- Voltage droop: V = L × dI/dt = 23.4e-9 × 3/1e-9 = 70V (!)
Analysis: 70V droop is impossible on a 1V supply — this shows why local decoupling is critical. Ruehli's formula gives the partial inductance of the trace on its own; a ground plane 0.2mm below cuts the loop inductance to roughly μ0 × h/w = 0.13 nH/mm (3.8 nH over 30mm), and even that still means 11V of droop. With a 10µF capacitor providing charge during the 1ns transient, actual droop is <50mV. Decoupling capacitor must be within 10mm of FPGA power pins.
Practical Tips
- ✓Use an adjacent ground plane for every signal layer — it minimizes loop inductance: a 0.3 mm trace has about 0.22 nH/mm with the plane 0.1 mm below, against 0.62 nH/mm at 1 mm (microstrip model). That is loop inductance; the partial inductance the calculator reports does not depend on the plane.
- ✓Add via stitching every 10mm along power traces — connects to internal ground planes, providing parallel return paths that reduce effective inductance by 30-50%.
- ✓For PDN design: target plane inductance <0.1 nH per square inch by using tight power-ground spacing (<0.1mm) per Smith's 'High-Speed Digital System Design'.
Common Mistakes
- ✗Ignoring trace inductance in power distribution — at 100 MHz, a 50 mm, 0.3 mm trace in 1 oz copper has 39.0 Ω of inductive reactance against 82 mΩ of DC resistance. Above about 210 kHz, its impedance is set by inductance, not resistance.
- ✗Widening a trace to cut its inductance — the partial inductance varies with ln(w + t), so doubling a 50 mm trace from 0.3 mm to 0.6 mm wide lowers it only from 62.0 nH to 55.6 nH, about 10%. Shortening the trace, adding a parallel path spaced well away, or bringing the return plane closer does much more.
- ✗Neglecting return path inductance — a signal trace's loop inductance includes the return current path. Ground plane slots or splits can double loop inductance and increase EMI by 6 dB.
Frequently Asked Questions
Related Articles
Shop Components
As an Amazon Associate we earn from qualifying purchases.
Related Calculators
PCB
Decoupling Capacitor
Calculate decoupling capacitor SRF, impedance at target frequency, and number of caps needed for power integrity. Includes ESR/ESL modeling. Free, instant results.
PCB
PCB Crosstalk
Calculate PCB trace crosstalk NEXT, FEXT, and coupling coefficient for signal integrity analysis. Determine critical length and guard trace spacing. Free, instant results.
PCB
Via Calculator
Calculate PCB via impedance, capacitance, inductance, and current capacity. Get aspect ratio and DFM warnings for through-hole and blind vias. Free, instant results.
PCB
Trace Width
Calculate minimum PCB trace width for current capacity per IPC-2221 and IPC-2152. Get resistance, voltage drop, and power dissipation. Free, instant results.