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PCB Trace Inductance Calculator

Calculate PCB trace parasitic inductance using the Ruehli formula. Get inductance per unit length and impedance at 100 MHz and 1 GHz. Free, instant results.

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Formula

L=(mu0l/2π)×[ln(2l/(w+t))+0.5+(w+t)/(3l)]L = (mu_0l / 2π) × [ln(2l/(w+t)) + 0.5 + (w+t)/(3l)]
L— Inductance (H)
mu_0— Permeability of free space (H/m)
l— Trace length (m)
w— Trace width (m)
t— Copper thickness (m)

How It Works

The PCB Trace Inductance Calculator computes the partial self-inductance of a straight, rectangular PCB trace from its length, width and copper thickness — essential for power distribution network (PDN) design, decoupling capacitor placement, and high-frequency signal integrity. Partial inductance is the trace's own share of the inductance of whatever loop its current flows in; at 100 MHz, every nanohenry of it between a capacitor and an IC pin adds 0.63 Ω of reactance. The calculator models the trace on its own: it has no input for the height above a ground plane, so it gives the same result for a microstrip, a stripline or a trace with no plane at all.

It uses Ruehli's closed form for a rectangular conductor: L=μ0l2π[ln⁡2lw+t+0.5+w+t3l]L = \frac{\mu_0 l}{2\pi}\left[\ln\frac{2l}{w+t} + 0.5 + \frac{w+t}{3l}\right], where l is the trace length, w the trace width and t the copper thickness. A 50 mm trace, 0.3 mm wide in 1 oz (35 µm) copper, comes to 62.0 nH, or 1.24 nH/mm. At 100 MHz that is 39.0 Ω of reactance, far above the trace's DC resistance of 82 mΩ.

Inductance dominates a trace's impedance above the crossover frequency fc=R/(2πL)f_c = R/(2\pi L), where R is its DC resistance. In 1 oz copper that is about 210 kHz for the 50 mm, 0.3 mm trace above, 50 kHz for the worked example's 30 mm, 2 mm power trace and 395 kHz for the calculator's default 10 mm, 0.2 mm trace. Above it, shortening a trace or adding parallel paths (copper pours) lowers impedance more than widening does: width enters only through the logarithm, while each parallel path divides the inductance, provided the paths are far enough apart that their mutual inductance is small.

Loop inductance is a different quantity, and the calculator does not report it. A trace's current returns through the reference plane beneath it, and what sets ground bounce and radiated emissions is the inductance of the whole loop: the closer the plane, the more of the trace's field the return current cancels. Per unit length, the loop inductance of a microstrip is L′=Z0εeff/cL' = Z_0\sqrt{\varepsilon_{eff}}/c, its impedance times its propagation delay per unit length, both of which the microstrip impedance calculator reports. For the 0.3 mm trace above, that is 0.62 nH/mm with the plane 1 mm below and 0.22 nH/mm at 0.1 mm, a 65% reduction, against 1.24 nH/mm of partial inductance. For a trace much wider than its height above the plane, L′≈μ0h/wL' \approx \mu_0 h/w is a quick estimate, as in the worked example; it reads somewhat high because it ignores the fringing field. This is why controlled impedance designs place signal layers next to ground planes.

Worked Example

Problem: Calculate the inductance of a 30mm power trace (2mm wide, 1oz copper) supplying a 1 GHz FPGA with a 3A transient current demand in 1ns.

Solution per Ruehli (the formula the calculator uses):

  1. Trace parameters: l = 30mm, w = 2mm, t = 35µm (1oz)
  2. Inductance: L = (μ0 × l / 2π) × [ln(2l/(w+t)) + 0.5 + (w+t)/(3l)]
  3. L = 2e-7 × 0.03 × [ln(0.06/0.002035) + 0.5 + 0.002035/0.09] = 6e-9 × [3.384 + 0.5 + 0.023] = 6e-9 × 3.907 = 23.4 nH
  4. Per unit length: 23.4 nH / 30mm = 0.78 nH/mm; reactance at 1 GHz = 2π × 1e9 × 23.4e-9 = 147Ω
  5. Voltage droop: V = L × dI/dt = 23.4e-9 × 3/1e-9 = 70V (!)

Analysis: 70V droop is impossible on a 1V supply — this shows why local decoupling is critical. Ruehli's formula gives the partial inductance of the trace on its own; a ground plane 0.2mm below cuts the loop inductance to roughly μ0 × h/w = 0.13 nH/mm (3.8 nH over 30mm), and even that still means 11V of droop. With a 10µF capacitor providing charge during the 1ns transient, actual droop is <50mV. Decoupling capacitor must be within 10mm of FPGA power pins.

Practical Tips

  • ✓Use an adjacent ground plane for every signal layer — it minimizes loop inductance: a 0.3 mm trace has about 0.22 nH/mm with the plane 0.1 mm below, against 0.62 nH/mm at 1 mm (microstrip model). That is loop inductance; the partial inductance the calculator reports does not depend on the plane.
  • ✓Add via stitching every 10mm along power traces — connects to internal ground planes, providing parallel return paths that reduce effective inductance by 30-50%.
  • ✓For PDN design: target plane inductance <0.1 nH per square inch by using tight power-ground spacing (<0.1mm) per Smith's 'High-Speed Digital System Design'.

Common Mistakes

  • ✗Ignoring trace inductance in power distribution — at 100 MHz, a 50 mm, 0.3 mm trace in 1 oz copper has 39.0 Ω of inductive reactance against 82 mΩ of DC resistance. Above about 210 kHz, its impedance is set by inductance, not resistance.
  • ✗Widening a trace to cut its inductance — the partial inductance varies with ln(w + t), so doubling a 50 mm trace from 0.3 mm to 0.6 mm wide lowers it only from 62.0 nH to 55.6 nH, about 10%. Shortening the trace, adding a parallel path spaced well away, or bringing the return plane closer does much more.
  • ✗Neglecting return path inductance — a signal trace's loop inductance includes the return current path. Ground plane slots or splits can double loop inductance and increase EMI by 6 dB.

Frequently Asked Questions

Inductance creates voltage noise V = L x dI/dt. For a 1A signal with 1ns edge on 20 nH trace, noise = 20V — clearly saturating any logic level. This is why decoupling capacitors (providing local charge) and short trace lengths are critical. Per JEDEC, PDN inductance must be <10 nH for DDR4 DIMM sockets.
For the partial inductance this calculator reports: (1) Trace length — slightly faster than linear, because the logarithm grows too; doubling a 0.3 mm trace from 50 mm to 100 mm raises it from 62.0 nH to 137.9 nH, 2.2 times. (2) Width and copper thickness — a weak, logarithmic effect through ln(w + t); doubling the width lowers it by only 10%. Height above a ground plane is not an input, but it dominates the loop inductance: moving the plane from 0.5 mm to 0.1 mm below a 0.3 mm trace cuts that from 0.49 nH/mm to 0.22 nH/mm, about 55%. Focus on short traces and a close return path, not on widening.
No — every conductor has inductance. A lone trace's partial inductance is roughly 1 nH/mm: the calculator gives 9.9 nH for its default 10 mm, 0.2 mm trace. A ground plane directly beneath does not change that figure, but it lowers the loop inductance, to about 0.22 nH/mm for a 0.3 mm trace 0.1 mm above its plane, and less for wider traces on thinner dielectric. Good layout makes it small, never zero.
It changes the loop inductance, not the partial inductance this calculator reports, which has no height input. Under a 0.3 mm trace, moving the plane from 1 mm to 0.1 mm below cuts the loop inductance from 0.62 nH/mm to 0.22 nH/mm, about 65%, by the Hammerstad-Jensen microstrip model. This is the main benefit of a controlled impedance stackup: the close reference plane keeps the impedance steady and the current loop small, which also improves EMC.
Per Johnson/Graham: approximately 1 nH per mm of via length. A through-hole via in 1.6mm board has 1.5-2.0 nH. Two ground vias adjacent to signal via reduce effective inductance to 0.8-1.0 nH by providing parallel return paths. Via inductance often dominates over trace inductance in high-speed paths.

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