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Via Step Response & Rise-Time Degradation Calculator

Model a PCB via as a lumped LC discontinuity: excess capacitance and inductance, self-resonant frequency, 10–90 % rise-time degradation, and peak reflection for a given edge rate.

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Formula

Δtr=2.2 Z02(C−LZ02),tr,out=tr,in2+Δtr2,f0=12πLC\Delta t_r = 2.2\,\frac{Z_0}{2}\left(C - \frac{L}{Z_0^{2}}\right), \qquad t_{r,\text{out}} = \sqrt{t_{r,\text{in}}^{2} + \Delta t_r^{2}}, \qquad f_0 = \frac{1}{2\pi\sqrt{LC}}

Reference: H. Johnson & M. Graham, "High-Speed Digital Design", Prentice Hall 1993; IPC-2141A (via capacitance)

L— Via barrel inductance (nH)
C— Pad-to-antipad capacitance (pF)
C_exc— Capacitance in excess of a matched section (pF)
Z₀— Impedance of the line the via sits in (Ω)
tᵣ— 10–90 % rise time (ps)
f₀— LC self-resonant frequency of the via (GHz)
f_knee— Knee frequency, 0.5/tᵣ (GHz)

How It Works

A via is short compared with the wavelength of any signal it is likely to carry, so it is modelled not as a transmission line but as a lumped discontinuity: one series inductance from the plated barrel and one shunt capacitance between the pad and the surrounding antipad. The barrel inductance follows the short-round-conductor form L=0.2h[ln⁡(4h/d)+0.5]L = 0.2 h [\ln(4h/d) + 0.5] nH with hh and dd in millimetres, and the pad-to-antipad capacitance follows IPC-2141A as C=0.0554εrhD1/(D2−D1)C = 0.0554 \varepsilon_r h D_1 / (D_2 - D_1) pF. Note that inductance grows with barrel length but only logarithmically with diameter — shortening a via helps far more than fattening it.

The crucial point is that neither LL nor CC alone tells you whether the via hurts. An ordinary section of transmission line also has inductance and capacitance; what a receiver actually sees is the imbalance between them. Subtract what a matched section would have contributed and you get the excess: Cexc=C−L/Z02C_{exc} = C - L/Z_0^2 and Lexc=L−CZ02L_{exc} = L - C Z_0^2. Exactly one of these is positive, and it identifies the character of the discontinuity. A via with L/C=Z0\sqrt{L/C} = Z_0 has zero excess and is electrically invisible no matter how large LL and CC are individually.

From the excess the timing cost follows directly. A small shunt capacitance is charged through the source impedance in parallel with the load, Z0/2Z_0/2, giving a first-order time constant τ=Z0Cexc/2\tau = Z_0 C_{exc}/2; converting to a 10–90 % edge multiplies by ln⁡9≈2.2\ln 9 \approx 2.2. A small series inductance gives τ=Lexc/2Z0\tau = L_{exc}/2Z_0 by the same argument. Cascaded first-order edges combine approximately in quadrature, so tr,out=tr,in2+Δtr2t_{r,out} = \sqrt{t_{r,in}^2 + \Delta t_r^2}. The consequence is that the same via is harmless on a slow edge and severe on a fast one: a 6 ps degradation costs 0.2 ps on a 100 ps edge but doubles a 6 ps edge.

Reflection behaves differently again. The peak reflected amplitude from a small discontinuity is ρ≈Z0Cexc/(2tr)\rho \approx Z_0 C_{exc}/(2 t_r) — inversely proportional to rise time, so it grows in direct proportion to edge rate rather than in quadrature. Finally, LL and CC resonate at f0=1/(2πLC)f_0 = 1/(2\pi\sqrt{LC}). This structural self-resonance is distinct from the λ/4\lambda/4 resonance of an unused barrel stub, and once the signal knee frequency 0.5/tr0.5/t_r approaches it the lumped model becomes optimistic.

Worked Example

Given: 1.6 mm through via, 0.3 mm drill, 0.6 mm pad, 1.0 mm antipad, εr=4.3\varepsilon_r = 4.3, in a 50 Ω line carrying a 400 ps LVDS edge Step 1: Barrel inductance L=0.2h[ln⁡4hd+0.5]=0.2×1.6×[ln⁡6.40.3+0.5]L = 0.2 h\left[\ln\frac{4h}{d} + 0.5\right] = 0.2 \times 1.6 \times \left[\ln\frac{6.4}{0.3} + 0.5\right] =0.32×[ln⁡(21.3333)+0.5]=0.32×[3.060271+0.5]=1.1392866543013003= 0.32 \times [\ln(21.3333) + 0.5] = 0.32 \times [3.060271 + 0.5] = 1.1392866543013003 nH Step 2: Pad-to-antipad capacitance C=0.0554 εr h D1D2−D1=0.0554×4.3×1.6×0.61.0−0.6=0.22869120.4=0.571728C = \frac{0.0554\,\varepsilon_r\, h\, D_1}{D_2 - D_1} = \frac{0.0554 \times 4.3 \times 1.6 \times 0.6}{1.0 - 0.6} = \frac{0.2286912}{0.4} = 0.571728 pF Step 3: Via impedance and self-resonance Zvia=L/C=1.1392867×10−90.571728×10−12=1992.71=44.63975208617234Z_{via} = \sqrt{L/C} = \sqrt{\frac{1.1392867 \times 10^{-9}}{0.571728 \times 10^{-12}}} = \sqrt{1992.71} = 44.63975208617234 Ω

Below 50 Ω, so this via is capacitive — the usual case for a large pad in a tight antipad.

f0=12πLC=12π×2.55218×10−11=6.236040048470675f_0 = \frac{1}{2\pi\sqrt{LC}} = \frac{1}{2\pi \times 2.55218 \times 10^{-11}} = 6.236040048470675 GHz Step 4: Excess reactance against a 50 Ω line Cexc=C−LZ02=5.71728×10−13−1.1392867×10−92500=5.71728×10−13−4.557147×10−13C_{exc} = C - \frac{L}{Z_0^2} = 5.71728 \times 10^{-13} - \frac{1.1392867 \times 10^{-9}}{2500} = 5.71728 \times 10^{-13} - 4.557147 \times 10^{-13} =1.1601334×10−13= 1.1601334 \times 10^{-13} F =0.11601333827947972= 0.11601333827947972 pF Lexc=L−CZ02=−0.2900333456986994L_{exc} = L - C Z_0^2 = -0.2900333456986994 nH — negative, confirming capacitive dominance.

Only 20 % of the raw 0.57 pF is actually a discontinuity; the rest is what a matched line of the same length would have had anyway.

Step 5: Rise-time degradation Δtr=2.2×Z02×Cexc=2.2×25×1.1601334×10−13=6.380733605371386\Delta t_r = 2.2 \times \frac{Z_0}{2} \times C_{exc} = 2.2 \times 25 \times 1.1601334 \times 10^{-13} = 6.380733605371386 ps tr,out=4002+6.3807342=160000+40.714=400.05088896457t_{r,out} = \sqrt{400^2 + 6.380734^2} = \sqrt{160000 + 40.714} = 400.05088896457 ps

An increase of only 0.0127 % — quadrature addition is very forgiving when the degradation is small relative to the edge.

Step 6: Reflection ρ=Z0Cexc2tr=50×1.1601334×10−132×400×10−12=0.0072508=0.7250833642467482 %\rho = \frac{Z_0 C_{exc}}{2 t_r} = \frac{50 \times 1.1601334 \times 10^{-13}}{2 \times 400 \times 10^{-12}} = 0.0072508 = 0.7250833642467482\ \%

The knee frequency is 0.5/400 ps=1.250.5/400\ \text{ps} = 1.25 GHz, comfortably below the 6.24 GHz self-resonance, so the lumped model is valid here.

Result: a negligible 0.05 ps of edge degradation and 0.73 % reflection at LVDS rates. Drop the edge to 30 ps and the same via reflects 9.7 % — the geometry did not change, only the spectrum did.

Practical Tips

  • ✓Aim for Z_via close to the line impedance rather than for minimum capacitance. The excess-capacitance output crossing zero is the optimum, and it is directly visible as you adjust the antipad
  • ✓Remove non-functional pads on layers the via does not connect to. This is usually the largest single reduction in via capacitance available and costs nothing in fabrication
  • ✓Back-drill long vias on high-speed nets. Shortening the barrel cuts inductance and capacitance together, which moves the self-resonance up rather than trading one for the other
  • ✓Check the knee frequency against the self-resonance before trusting any lumped via model. If the knee is within about a third of f0, only a 3D field solver will give a reliable answer
  • ✓For differential pairs, model each via of the pair separately at the single-ended impedance — a 100 ohm differential pair has 50 ohm single-ended lines, so use 50 ohms here

Common Mistakes

  • ✗Judging a via by its raw capacitance — 0.57 pF sounds alarming, but four fifths of it is matched by the barrel inductance and only the 0.12 pF excess is a discontinuity. Compare against L/Z0-squared, not against zero
  • ✗Maximising the antipad diameter on the assumption that less capacitance is always better — push C below L/Z0-squared and the via flips inductive and the reflection climbs again. Growing the default antipad from 1.0 to 2.0 mm makes the reflection worse, from 2.9 percent to 7.3 percent at a 100 ps edge
  • ✗Designing to clock frequency rather than edge rate — a 100 MHz clock with a 50 ps edge stresses a via far harder than a 500 MHz clock with a 500 ps edge, because both reflection and degradation track the rise time
  • ✗Confusing this LC self-resonance with the via stub quarter-wave resonance — they are different mechanisms with different frequencies, and the stub resonance is usually the lower and more damaging of the two
  • ✗Using board thickness for the barrel length on a back-drilled via — after back-drilling the signal only traverses the remaining stub-free length, and using the full thickness overstates both L and C substantially

Frequently Asked Questions

Rise times combine in quadrature. A 6 ps degradation on a 400 ps edge gives 400.05 ps, a 0.01 percent effect. The same 6 ps on a 20 ps edge gives 20.9 ps, a 4.5 percent effect. Reflection is worse still because it scales as 1 over the rise time directly, not in quadrature, so it grows twenty-fold over that same range.
A matched transmission line of the same physical length also has capacitance, and that portion costs nothing because it is part of a properly terminated line. Only the amount beyond L divided by Z0 squared is a discontinuity. A via with square root of L over C equal to 50 ohms has zero excess and is electrically invisible in a 50 ohm system.
Enlarge the antipad, remove non-functional pads on unused layers, and shrink the pad to the minimum annular ring the fabricator allows. But stop at C equal to L divided by Z0 squared — going further makes the via inductive and the reflection rises again. Watch the excess-capacitance output cross zero.
No. The quarter-wave stub resonance comes from an unused length of barrel acting as an open transmission line, producing a deep narrow insertion-loss null. The f0 here is the lumped LC self-resonance of the via structure itself. Both should stay well above your knee frequency, and the stub resonance is usually the lower one.
When the via is no longer electrically short compared to the signal — practically, when the knee frequency reaches about a third of the LC self-resonance, or when the computed reflection exceeds roughly 30 percent. Past that point L and C interact as a distributed structure. The calculator warns in both cases.
IPC-2141A treats the via as a coaxial section spanning the layers it passes through, so the barrel length sets the plate area. If your via only crosses two planes rather than a full stack-up, use the length between those planes instead of the board thickness — the result scales linearly with it.

Related Articles

Signal Integrity

A Via Is Not a Capacitor: Excess Reactance and Rise Time

Via capacitance sounds alarming until you subtract what a matched line would have had anyway. Only the excess is a discontinuity — and shrinking capacitance past the optimum makes reflection worse, not better.

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