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Via Voltage Drop & Power Calculator

Calculate DC resistance, voltage drop, and power dissipation of plated through-hole vias with temperature compensation and parallel via arrays.

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Formula

R=ρ0[1+α(T−20)] Lπ t (D−t)R = \frac{\rho_0 [1 + \alpha(T-20)]\, L}{\pi\, t\,(D - t)}
R— Via resistance (Ω)
ρ₀— Copper resistivity at 20°C (1.724×10⁻⁸) (Ω·m)
α— Temperature coefficient (0.00393) (/°C)
L— Via barrel length (m)
t— Plating thickness (m)
D— Drill diameter (m)

How It Works

A plated through-hole via has finite DC resistance determined by the copper barrel geometry. The cross-section is a thin-wall annular cylinder: area = π × t × (D − t), where D is the drill diameter and t is the plating thickness (typically 18–25 µm per IPC-6012 Class 2). This small cross-section means a single via has milliohm-level resistance that matters in high-current power distribution.

Copper resistivity increases with temperature at 0.393%/°C (α = 0.00393/°C). At 85°C operating temperature, resistance is 26% higher than at 20°C. This temperature dependence is critical for power integrity analysis because the via heats up under load, increasing its resistance, which increases heating further — a positive feedback loop limited by thermal conduction to surrounding copper.

Parallel via arrays divide the total resistance by N (number of vias). Eight 0.3 mm vias in parallel through a 1.6 mm board have roughly 0.33 mΩ total resistance — comparable to a few millimetres of trace. Power converter designs routinely use 4–20 parallel vias per power rail transition between layers.

Worked Example

Given: Drill diameter = 0.3 mm, plating thickness = 25 µm, via length = 1.6 mm (board thickness), current = 1 A, temperature = 25°C, single via Step 1: Copper resistivity at temperature ρ=ρ20×[1+α(T−20)]=1.724×10−8×[1+0.00393×5]=1.758×10−8\rho = \rho_{20} \times [1 + \alpha(T-20)] = 1.724 \times 10^{-8} \times [1 + 0.00393 \times 5] = 1.758 \times 10^{-8} Ω·m Step 2: Via cross-sectional area D=0.3×10−3D = 0.3 \times 10^{-3} m, t=25×10−6t = 25 \times 10^{-6} m A=π×t×(D−t)=π×25×10−6×(300−25)×10−6A = \pi \times t \times (D - t) = \pi \times 25 \times 10^{-6} \times (300 - 25) \times 10^{-6} =π×25×275×10−12=21.6×10−9= \pi \times 25 \times 275 \times 10^{-12} = 21.6 \times 10^{-9} m² = 0.0216 mm² Step 3: Single via resistance R=ρ×LA=1.758×10−8×1.6×10−321.6×10−9=1.30R = \frac{\rho \times L}{A} = \frac{1.758 \times 10^{-8} \times 1.6 \times 10^{-3}}{21.6 \times 10^{-9}} = 1.30 mΩ Step 4: Voltage drop and power Vdrop=I×R=1.0×1.30×10−3=1.30V_{drop} = I \times R = 1.0 \times 1.30 \times 10^{-3} = 1.30 mV P=I2×R=1.02×1.30×10−3=1.30P = I^2 \times R = 1.0^2 \times 1.30 \times 10^{-3} = 1.30 mW Step 5: Temperature rise estimate θvia=LkCu×A=1.6×10−3385×21.6×10−9=192\theta_{via} = \frac{L}{k_{Cu} \times A} = \frac{1.6 \times 10^{-3}}{385 \times 21.6 \times 10^{-9}} = 192 °C/W ΔT=P×θ=1.30×10−3×192=0.25\Delta T = P \times \theta = 1.30 \times 10^{-3} \times 192 = 0.25 °C (negligible) Result: 1.30 mΩ resistance, 1.30 mV drop at 1A — negligible for most applications.

Practical Tips

  • ✓Use 8–12 parallel vias for each amp of continuous current to keep temperature rise under 5°C
  • ✓Place power vias directly under component pads (via-in-pad) to minimise trace length between via and load
  • ✓For PDN analysis tools, model each via as a series resistance + inductance (typically 0.5–1 nH per via)
  • ✓Larger drill diameter helps more than thicker plating — area scales as D×t, so doubling D doubles the area while doubling t only adds t
  • ✓In thermal via arrays (for heat dissipation), the thermal resistance matters more than electrical — fill with copper or thermal paste for better conductivity

Common Mistakes

  • ✗Assuming via resistance is zero — at 20A through a single via, the drop is 26 mV and dissipation is 520 mW, causing real thermal issues
  • ✗Using the full drill area (πD²/4) instead of the thin-wall annulus — solid copper fills are rare; standard vias are hollow barrels with 25 µm plating
  • ✗Ignoring temperature coefficient — a power via at 85°C has 26% more resistance than at 20°C; always calculate at worst-case operating temperature
  • ✗Counting on nominal plating thickness — IPC-6012 minimum is 18 µm; design with minimum plating for worst-case resistance

Frequently Asked Questions

Rule of thumb: 1A per standard via (0.3 mm drill, 25 µm plating) keeps temperature rise under 5°C. For 5A: use at least 5 vias, preferably 8 for margin. Larger vias (0.4–0.5 mm) carry proportionally more current.
Yes — resistance is proportional to length. A 3.2 mm board has 2× the via resistance of a 1.6 mm board. For thick boards with high current, use larger drills or more parallel vias to compensate.
Copper-filled vias have much lower resistance (solid cross-section vs. thin-wall annulus) but are expensive. For high-current applications (> 10A per via), they're justified. For standard 1–5A transitions, parallel standard vias are more cost-effective.
A single 0.3 mm via through 1.6 mm board ≈ 1.3 mΩ. A 10 mm long, 0.25 mm wide trace on 1 oz copper ≈ 19.7 mΩ. The via is typically 10–15× lower resistance than the connecting trace — trace resistance usually dominates.
Via inductance (0.5–1 nH) is often more significant than via resistance for power integrity at MHz frequencies. At 100 MHz, 1 nH has 628 mΩ impedance vs. 1.3 mΩ DC resistance. Parallel vias reduce both R and L.

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