Documentation sections
SPI Timing & Signal Integrity Calculator
POSThttps://rftools.io/ api/ py/ v1/ calculate
Slug spi-timing. Calculate SPI bus timing parameters including bit period, frame time, maximum clock frequency limited by trace capacitance, and signal slew rate
Inputs
Send every one of these in inputs, in the units shown. Most are required: a call without one is refused (400) and costs nothing; one the calculator can do without takes the default shown. An input outside its range is still computed and flagged in the provenance.
| Name | Unit | Range | Default | Description |
|---|---|---|---|---|
| clockFreqnumber | MHz | at least 0.001 | 10 | SPI SCLK frequency in MHz |
| dataWidthnumber | bits | 1 … 32 | 8 | Number of data bits per SPI frame |
| traceCapacitancenumber | pF | at least 0.1 | 20 | Estimated total capacitive load on the signal line (PCB trace + receiver) |
| driveStrengthnumber | mA | at least 0.1 | 4 | GPIO output drive current capability in mA |
Outputs
Returned in values, by key. A value that is unbounded or undefined is null.
| Field | Unit | Description |
|---|---|---|
| bitPeriod | ns | Bit Period |
| framePeriod | μs | Frame Period |
| maxFreqCapacitiveheadline | MHz | Max Freq (RC-limited) |
| slewRate | V/ns | Signal Slew Rate |
| dataRate | Mbps | Data Rate |
| riseTime | ns | 2.2τ, the 10–90 % rise of the RC charge through the calculator's drive model, R = 3.3 V / I_drive (825 Ω at 4 mA); a CMOS output is usually stiffer than that (V_OL / I_OL), so this edge is a slow bound |
| edgeShare_pct | % | How much of the half period the edge takes before the sampling edge; 100 % at the RC-limited maximum |
Calling it
- Calculate: one call, the request and response in full, and its errors.
- Batch: this calculator with others, or a sweep, in one request.
- Solve for a target: the value of one input that brings an output to a target.