PCB Design Calculators
36 free calculators with formulas and worked examples.
Trace width, controlled impedance, via sizing, differential pairs, crosstalk, decoupling, and PCB thermal calculators for high-speed and high-power board design.
Trace Width
Calculate minimum PCB trace width for current capacity per IPC-2221 and IPC-2152’s conservative Figure 5-1. Get resistance, voltage drop, and power dissipation at the width you draw. Free, instant results.
Trace Resistance
Calculate PCB copper trace DC resistance from width, length, thickness, and temperature. Get sheet resistance and temp coefficient. Free, instant results.
Differential Pair
Calculate Zdiff and Zcommon for edge-coupled microstrip pairs. Design USB, HDMI, and Ethernet differential pairs with odd/even mode impedance. Free, instant results.
Via Calculator
Calculate PCB via impedance, capacitance, inductance, and current capacity. Get aspect ratio and DFM warnings for through-hole and blind vias. Free, instant results.
Stackup Builder
Calculate trace widths for a target impedance on a 4-layer PCB stackup: microstrip on L1 over the L2 plane, stripline on L3 between the L2 and L4 planes. Enter the dielectric heights, dielectric constant and copper weight for 50 ohm or a custom Z0. Free, instant results.
Controlled Z
Calculate characteristic impedance for surface microstrip, embedded microstrip, and stripline PCB traces. Get Z0, effective Er, and target trace width. Free, instant results.
PCB Crosstalk
Calculate PCB trace crosstalk NEXT, FEXT, and coupling coefficient for signal integrity analysis. Determine critical length and guard trace spacing. Free, instant results.
Decoupling Capacitor
Calculate decoupling capacitor SRF, impedance at target frequency, and number of caps needed for power integrity. Includes ESR/ESL modeling. Free, instant results.
PCB Trace Inductance
Calculate PCB trace parasitic inductance using the Ruehli formula. Get inductance per unit length and impedance at 100 MHz and 1 GHz. Free, instant results.
Via Thermal Resistance
Calculate thermal via resistance, array conductance, and current capacity for PCB thermal management. Design filled and plated via arrays. Free, instant results.
Power Plane Impedance
Calculate PCB power plane impedance, capacitance, inductance, and resonant frequency for PDN design. Optimize your power delivery network. Free, instant results.
Via Stub Resonance
Calculate via stub resonant frequency, signal notch depth, and backdrill benefit for high-speed PCB design. Optimize stub length. Free, instant results.
Solder Paste Volume
Calculate solder paste volume, stencil aperture area, and IPC-7525A area ratio. Design SMD stencils for reliable reflow soldering. Free, instant results.
Asymmetric Stripline
Calculate the characteristic impedance of an offset (asymmetric) stripline where the trace sits closer to one reference plane than the other. Compares against the centred case.
Dual Stripline
Calculate impedance for both signal layers of a dual stripline (two routing layers sharing one plane pair), plus the broadside crosstalk penalty when traces overlap.
Broadside Pair
Calculate differential and common-mode impedance for a broadside-coupled pair — two traces stacked on adjacent layers — for both shielded (between planes) and unshielded geometries.
Edge-Coupled Stripline
Calculate differential, common-mode, odd- and even-mode impedance for an edge-coupled differential pair centred between two reference planes. Exact conformal-mapping solution, not an empirical fit.
Offset Coupled Stripline
Calculate differential and common-mode impedance for an edge-coupled pair sitting off-centre between two reference planes — the usual case in an asymmetric stack-up.
Coupled Embedded Microstrip
Calculate differential and common-mode impedance for an edge-coupled pair under soldermask, coating or prepreg — with a separate effective permittivity per mode, so the skew the cover introduces is visible.
Differential Via
Calculate differential impedance and insertion loss for a via pair, including the stub resonance that dominates a via transition long before conductor and dielectric loss matter.
Skin Depth %
Express skin depth as a percentage of trace thickness and get the AC/DC resistance ratio that follows, so you can tell whether a copper weight choice still matters at your frequency.
Conductor to Pad
Find the widest conductor that can reach a pad through the channel between its neighbours, from pad diameter, pitch and your fabricator’s minimum clearance.
BGA Breakout
Find the widest escape trace that fits between BGA lands from ball pitch, land diameter, your fabricator’s clearance and the number of traces per channel — and whether it fits at all.
Aperture Diagonal
Get the corner-to-corner diagonal of a rectangular aperture plus the stocked tool that covers it — the drill that clears the diagonal, or the cutter that fits the short side and the corner radius it leaves.
Max Pad Diameter
Find the largest pad that fits a component pitch while holding your fabricator’s clearance, with or without conductors routed between adjacent pads.
Critical Length
Find the maximum PCB trace length before transmission-line effects matter. Compares your trace against Bogatin's 20% and 3× rise-time criteria and reports propagation delay.
Fusing Current
Calculate the current that will fuse a PCB trace using Onderdonk's equation. Includes etch-factor trapezoid correction, time-to-fuse at your operating current, and safety margin.
Annular Ring
Calculate minimum pad diameter and annular ring per IPC-6012 for through-hole vias and component pads.
BGA Land Pad
Calculate BGA land pad diameter, solder mask opening, and escape routing per IPC-7351B density levels.
Conductor Spacing
Determine minimum electrical clearance between conductors per IPC-2221B Table 6.1 based on voltage and conductor condition.
Spiral Inductor
Calculate PCB planar spiral inductance using Mohan current-sheet and modified Wheeler methods for square, hexagonal, octagonal, and circular geometries.
Embedded Resistor
Calculate geometry for PCB embedded resistors from target resistance and sheet resistance. Supports NiP, TaN, CrSiO, and carbon materials.
Via Voltage Drop
Calculate DC resistance, voltage drop, and power dissipation of plated through-hole vias with temperature compensation and parallel via arrays.
Effective Dielectric Constant
Calculate microstrip effective dielectric constant εeff with Hammerstad–Jensen, plus Getsinger dispersion, propagation velocity, delay in ps/mm and ps/inch, and guided wavelength.
Via Step Response
Model a PCB via as a lumped LC discontinuity: excess capacitance and inductance, self-resonant frequency, 10–90 % rise-time degradation, and peak reflection for a given edge rate.
Microvia Current
Calculate laser-drilled microvia current capacity from barrel cross-section using IPC-2221, with DC resistance, voltage drop, current density, self-heating, and IPC-2226 aspect-ratio checks.
About PCB Design Calculators
Printed circuit board design transforms schematic intent into manufacturable hardware, but high-speed and high-frequency signals impose constraints that go far beyond routing copper traces. At gigahertz frequencies or high slew rates, every trace is a transmission line, every via is an inductor, and every power plane gap is an antenna.
Controlled impedance is the first discipline: microstrip and stripline traces must be dimensioned to hit target impedances (typically 50 Ω single-ended, 100 Ω differential) within ±10%, otherwise signal reflections degrade eye diagrams and increase bit error rates. Trace width is determined by substrate thickness, dielectric constant, and copper weight — this calculator codifies the IPC-2141 and Hammerstad-Jensen equations that PCB fabricators use.
Current capacity is the second concern. IPC-2152 defines how wide a trace must be to carry a given current without exceeding a temperature rise budget. External traces dissipate heat more efficiently than internal ones, so the same 1 A requires a wider internal trace. Via sizing follows similar logic: a via with too small a barrel diameter becomes a thermal and electrical bottleneck.
Differential pairs require tight spacing control to maintain common-mode rejection. Decoupling capacitors must be placed within a few millimeters of IC power pins, with short low-inductance connections to the power plane. These calculators turn the IPC standards and electromagnetic field equations into immediately actionable numbers.
Advanced Simulation Tools
Eye Diagram from S-Parameters
Upload a Touchstone (.s2p) file and generate a PRBS eye diagram. Shows the channel insertion loss and impulse response, then renders the eye with its height, width and jitter measured over the whole bit sequence.
FDTD Transmission Line Simulator
Solve microstrip stubs, coupled-line filters, via transitions, and step discontinuities across a ladder of named solve modes — from a 2D cross-section in seconds to a fine 3D openEMS field solve. S-parameters, Smith chart, and impedance analysis.
PDN Impedance Analyzer & Decoupling Capacitor Optimizer
Choose decoupling capacitors for a PCB power delivery network. Enter the plane pair, the regulator and a flat target impedance, and a genetic algorithm finds the capacitor mix that keeps Z_PDN lowest across the decoupling band, which ends at 0.8 × the board's first cavity mode. Above the band the plane-pair cavity sets the impedance; the plot shows its resonances as one observation port sees them, with every capacitor lumped at that port.
S-Parameter Analysis Pipeline
Upload up to 4 Touchstone files and get component values (L, C, R, Q, self-resonance) for a single component, plus insertion loss, return loss, group delay, TDR and passband ripple — all in one automated report.